-
EP1246121
European procedure
Extract from the Register of European Patents
EP Citations: EP1246121
| Cited in | Search | Type: | Patent literature | Publication No.: | US5519811
[A] (YONEDA HIDEKI [US], et al) [A] 1-71 * the whole document *; | Type: | Non-patent literature | Publication information: | [A] - B. SHI, "Focal plane implementation of 2D steerable and scalable Gabor-type filters", JOURNAL OF VLSI SIGNAL PROCESSING, (1999), vol. 23, pages 319 - 334, XP002449041 [A] 1-71 * Section 4. 2D circuit architecture - Section 6.Transistor level circuit implementation * | DOI: | http://dx.doi.org/10.1023/A:1008197102693 | Type: | Non-patent literature | Publication information: | [A] - C. MEAD AND T. DELBRÜCK, "Scanners for visualizing activity of analog VLSI circuitry", ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, (1991), vol. 1, pages 93 - 106, XP008083017 [A] 1-71 * the whole document * | Type: | Non-patent literature | Publication information: | [A] - BEERHOLD J R ET AL, "Pulse-processing neural net hardware with selectable topology and adaptive weights and delays", PROC. INT. JOINT CONF. ON NEURAL NETWORKS, (19900617), pages 569 - 574, XP010006799 [A] 1-71 * the whole document * | Cited in | by applicant | Type: | Patent literature | Publication No.: | US5519811
| Type: | Patent literature | Publication No.: | JP2741793B
| Type: | Patent literature | Publication No.: | JP2000181487
| Type: | Non-patent literature | Publication information: | - B. SHI, "Focal plane implementation of 2D steerable and scalable Gabor-type filters", JOURNAL OF VLSI SIGNAL PROCESSING, (1999), vol. 23, pages 319 - 334 | Type: | Non-patent literature | Publication information: | - C. MEAD; T. DEIBRUCK, "Scanners for visualizing activity of analog VLSI circuitry", ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, (1991), vol. 1, pages 93 - 106 | Type: | Non-patent literature | Publication information: | - BEERHOLD J R ET AL., "Pulse-processing neural net hardware with selectable topology and adaptive weights and delays", PROC. INT. JOINT CONF. ON NEURAL NETWORKS, (19900617), pages 569 - 574 | Type: | Non-patent literature | Publication information: | - IEEE TRANS. ON NEURAL NETWORKS, vol. 10, page 540 | Type: | Non-patent literature | Publication information: | - TOMITA, Parallel Computer Configuration Theory, SHOKODO, (1986), pages 190 - 192 | Type: | Non-patent literature | Publication information: | - S.Y. KUNG, Digital Neural Networks, PTR PRENTICE HALL, (1993), pages 340 - 361 |