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EP1246121
European procedure
Extract from the Register of European Patents
EP About this file: EP1246121
| EP1246121 - Dynamically reconfigurable signal processing circuit, pattern recognition apparatus, and image processing apparatus [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 25.10.2013 Database last updated on 28.09.2024 | Most recent event Tooltip | 13.12.2013 | Lapse of the patent in a contracting state New state(s): IT | published on 15.01.2014 [2014/03] | Applicant(s) | For all designated states CANON KABUSHIKI KAISHA 3-30-2, Shimomaruko, Ohta-ku Tokyo / JP | [2012/51] |
| Former [2002/40] | For all designated states CANON KABUSHIKI KAISHA 3-30-2 Shimomaruko Ohta-ku, Tokyo / JP | Inventor(s) | 01 /
Matsugu, Masakazu Canon Kabushiki Kaisha 30-2, Shimomaruko 3-chome Ohta-ku, Tokyo / JP | 02 /
Mori, Katsuhiko Canon Kabushiki Kaisha 30-2, Shimomaruko 3-chome Ohta-ku, Tokyo / JP | 03 /
Nomura, Osamu Canon Kabushiki Kaisha 30-2, Shimomaruko 3-chome Ohta-ku, Tokyo / JP | [2012/51] |
| Former [2002/40] | 01 /
Matsugu, Masakazu Canon Kabushiki Kaisha, 30-2, Shimomaruko 3-chome Ohta-ku, Tokyo / JP | ||
| 02 /
Mori, Katsuhiko Canon Kabushiki Kaisha, 30-2, Shimomaruko 3-chome Ohta-ku, Tokyo / JP | |||
| 03 /
Nomura, Osamu Canon Kabushiki Kaisha, 30-2, Shimomaruko 3-chome Ohta-ku, Tokyo / JP | Representative(s) | Hitching, Peter Matthew, et al Canon Europe Ltd European Patent Department 3 The Square Stockley Park Uxbridge Middlesex UB11 1ET / GB | [N/P] |
| Former [2012/51] | Hitching, Peter Matthew, et al Canon Europe Ltd 3 The Square Stockley Park Uxbridge Middlesex UB11 1ET / GB | ||
| Former [2008/41] | Hitching, Peter Matthew, et al Canon Europe Limited 6 Roundwood Avenue Stockley Park Uxbridge UB11 1JA / GB | ||
| Former [2008/24] | Hitching, Peter Matthew, et al Canon Europe Ltd. European Patent Department 6 Roundwood Avenue Stockley Park Middlesex, Uxbridge UB11 1JA / GB | ||
| Former [2002/40] | Beresford, Keith Denis Lewis, et al BERESFORD & Co. 2-5 Warwick Court, High Holborn London WC1R 5DH / GB | Application number, filing date | 02252197.5 | 27.03.2002 | [2002/40] | Priority number, date | JP20010093274 | 28.03.2001 Original published format: JP 2001093274 | JP20010164510 | 31.05.2001 Original published format: JP 2001164510 | JP20010164282 | 31.05.2001 Original published format: JP 2001164282 | JP20010272557 | 07.09.2001 Original published format: JP 2001272557 | JP20010272555 | 07.09.2001 Original published format: JP 2001272555 | [2002/40] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP1246121 | Date: | 02.10.2002 | Language: | EN | [2002/40] | Type: | A3 Search report | No.: | EP1246121 | Date: | 10.10.2007 | [2007/41] | Type: | B1 Patent specification | No.: | EP1246121 | Date: | 19.12.2012 | Language: | EN | [2012/51] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 11.09.2007 | Classification | IPC: | G06K9/46, G06K9/00 | [2012/31] | CPC: |
G06V40/171 (EP,US);
G06V10/454 (EP,US);
G06V10/94 (EP,US);
G06N3/049 (EP,US);
G06N3/063 (EP,US)
|
| Former IPC [2002/40] | G06K9/00 | Designated contracting states | DE, FR, GB, IT, NL [2008/25] |
| Former [2002/40] | AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE, TR | Title | German: | Dynamisch rekonfigurierbare Schaltung zur Signalverarbeitung, Gerät zur Mustererkennung und Gerät zur Bildverarbeitung | [2002/40] | English: | Dynamically reconfigurable signal processing circuit, pattern recognition apparatus, and image processing apparatus | [2002/40] | French: | Circuit dynamiquement reconfigurable de traitement du signal, appareil de reconnaissance des formes et appareil de traitement des images | [2002/40] | Examination procedure | 10.04.2008 | Examination requested [2008/22] | 11.04.2008 | Loss of particular rights, legal effect: designated state(s) | 09.06.2008 | Despatch of communication of loss of particular rights: designated state(s) AT, BE, CH, CY, DK, ES, FI, GR, IE, LU, MC, PT, SE, TR | 11.01.2010 | Despatch of a communication from the examining division (Time limit: M06) | 30.08.2010 | Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time | 05.11.2010 | Reply to a communication from the examining division | 06.02.2012 | Despatch of a communication from the examining division (Time limit: M04) | 14.06.2012 | Reply to a communication from the examining division | 09.07.2012 | Communication of intention to grant the patent | 07.11.2012 | Fee for grant paid | 07.11.2012 | Fee for publishing/printing paid | Divisional application(s) | The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is 11.01.2010 | Opposition(s) | 20.09.2013 | No opposition filed within time limit [2013/48] | Request for further processing for: | The application is deemed to be withdrawn due to failure to reply to the examination report | 05.11.2010 | Request for further processing filed | 05.11.2010 | Full payment received (date of receipt of payment) Request granted | 17.11.2010 | Decision despatched | Fees paid | Renewal fee | 26.03.2004 | Renewal fee patent year 03 | 18.03.2005 | Renewal fee patent year 04 | 31.03.2006 | Renewal fee patent year 05 | 02.04.2007 | Renewal fee patent year 06 | 31.03.2008 | Renewal fee patent year 07 | 31.03.2009 | Renewal fee patent year 08 | 31.03.2010 | Renewal fee patent year 09 | 31.03.2011 | Renewal fee patent year 10 | 31.03.2012 | Renewal fee patent year 11 |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | IT | 19.12.2012 | NL | 19.12.2012 | [2014/03] |
| Former [2013/37] | NL | 19.12.2012 | Documents cited: | Search | [A]US5519811 (YONEDA HIDEKI [US], et al) [A] 1-71 * the whole document *; | [A] - B. SHI, "Focal plane implementation of 2D steerable and scalable Gabor-type filters", JOURNAL OF VLSI SIGNAL PROCESSING, (1999), vol. 23, pages 319 - 334, XP002449041 [A] 1-71 * Section 4. 2D circuit architecture - Section 6.Transistor level circuit implementation * DOI: http://dx.doi.org/10.1023/A:1008197102693 | [A] - C. MEAD AND T. DELBRÜCK, "Scanners for visualizing activity of analog VLSI circuitry", ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, (1991), vol. 1, pages 93 - 106, XP008083017 [A] 1-71 * the whole document * | [A] - BEERHOLD J R ET AL, "Pulse-processing neural net hardware with selectable topology and adaptive weights and delays", PROC. INT. JOINT CONF. ON NEURAL NETWORKS, (19900617), pages 569 - 574, XP010006799 [A] 1-71 * the whole document * | by applicant | US5519811 | JP2741793B | JP2000181487 | - B. SHI, "Focal plane implementation of 2D steerable and scalable Gabor-type filters", JOURNAL OF VLSI SIGNAL PROCESSING, (1999), vol. 23, pages 319 - 334 | - C. MEAD; T. DEIBRUCK, "Scanners for visualizing activity of analog VLSI circuitry", ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, (1991), vol. 1, pages 93 - 106 | - BEERHOLD J R ET AL., "Pulse-processing neural net hardware with selectable topology and adaptive weights and delays", PROC. INT. JOINT CONF. ON NEURAL NETWORKS, (19900617), pages 569 - 574 | - IEEE TRANS. ON NEURAL NETWORKS, vol. 10, page 540 | - TOMITA, Parallel Computer Configuration Theory, SHOKODO, (1986), pages 190 - 192 | - S.Y. KUNG, Digital Neural Networks, PTR PRENTICE HALL, (1993), pages 340 - 361 |