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Extract from the Register of European Patents

EP About this file: EP0939445

EP0939445 - Semiconductor integrated circuit device and method of arranging functional cell [Right-click to bookmark this link]
StatusThe application has been withdrawn
Status updated on  18.07.2003
Database last updated on 25.09.2024
Most recent event   Tooltip18.07.2003Withdrawal of applicationpublished on 03.09.2003  [2003/36]
Applicant(s)For all designated states
NEC Electronics Corporation
1753 Shimonumabe Nakahara-ku
Kawasaki, Kanagawa 211-8668 / JP
[N/P]
Former [2003/18]For all designated states
NEC Electronics Corporation
1753 Shimonumabe, Nakahara-ku
Kawasaki, Kanagawa 211-8668 / JP
Former [1999/35]For all designated states
NEC CORPORATION
7-1, Shiba 5-chome, Minato-ku
Tokyo / JP
Inventor(s)01 / Harayama, Masahiro c/o NEC IC Micro PC Syst., Ltd.
403-53, Kosugimachi 1-chome, Nakahara-ku
Kawasaki-shi, Kanagawa / JP
[1999/35]
Representative(s)Glawe, Delfs, Moll
Partnerschaft mbB von
Patent- und Rechtsanwälten
Postfach 26 01 62
80058 München / DE
[N/P]
Former [1999/35]Glawe, Delfs, Moll & Partner
Patentanwälte Postfach 26 01 62
80058 München / DE
Application number, filing date99103677.325.02.1999
[1999/35]
Priority number, dateJP1998004565226.02.1998         Original published format: JP 4565298
[1999/35]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0939445
Date:01.09.1999
Language:EN
[1999/35]
Type: A3 Search report 
No.:EP0939445
Date:24.10.2001
[2001/43]
Search report(s)(Supplementary) European search report - dispatched on:EP10.09.2001
ClassificationIPC:H01L27/118, H01L27/02
[2001/43]
CPC:
H01L27/118 (EP,US); H01L27/10 (KR)
Former IPC [1999/35]H01L27/118
Designated contracting statesDE,   FR,   GB [2002/29]
Former [1999/35]AT,  BE,  CH,  CY,  DE,  DK,  ES,  FI,  FR,  GB,  GR,  IE,  IT,  LI,  LU,  MC,  NL,  PT,  SE 
TitleGerman:Halbleiter integriertes Schaltkreisbauelement und Anordnungsverfahren für Funktionszellen[1999/35]
English:Semiconductor integrated circuit device and method of arranging functional cell[1999/35]
French:Dispositif de circuit intégré à semi-conducteur et le procédé d'arrangement de cellule fonctionnelle[1999/35]
Examination procedure30.10.2001Examination requested  [2002/01]
10.07.2003Application withdrawn by applicant  [2003/36]
Fees paidRenewal fee
15.02.2001Renewal fee patent year 03
15.02.2002Renewal fee patent year 04
20.02.2003Renewal fee patent year 05
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[X]GB2018021  (RACAL MICROELECT SYSTEM) [X] 1-3,6,8,11 * page 1, line 16 - line 43 * * page 1, line 82; figure 1 *;
 [X]WO8500468  (ADVANCED MICRO DEVICES INC [US]) [X] 1-3,6-8,11 * abstract * * page 6, line 6 - line 25; figure 1 ** page 6, line 26 - line 34; figure 2 *;
 [XA]US5444275  (KUGISHIMA MASAHIRO [JP], et al) [X] 1-3,6-8,11 * column 5, line 43 - line 55; figures 3A,10 * * column 8, line 14 - line 29; figures 21,22 * [A] 4,5,9,10;
 [XA]US5517041  (TORII KENSUKE [JP], et al) [X] 1-3,6-8,11 * abstract * * column 2, line 12 - line 20 * * column 5, line 56 - column 6, line 26 * * column 6, line 59 - column 7, line 2; figure 2 * [A] 4,5,9,10
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.