Extract from the Register of European Patents

About this file: EP1022571

EP1022571 - Apparatus and method for testing electric conductivity of circuit pathways on circuit board [Right-click to bookmark this link]
StatusThe application has been withdrawn
Status updated on  18.01.2002
Database last updated on 15.02.2019
Most recent event   Tooltip18.01.2002Withdrawal of applicationpublished on 06.03.2002  [2002/10]
Applicant(s)For all designated states
Nihon Densan Read Kabushiki Kaisha, (Nidec-Read Corporation)
126, Megawa, Makishima-cho Uji-city
Kyoto 611-0041 / JP
[N/P]
Former [2000/30]For all designated states
Nihon Densan Read Kabushiki Kaisha, (Nidec-Read Corporation)
126, Megawa, Makishima-cho
Uji-city, Kyoto 611-0041 / JP
Inventor(s)01 / Yamashita, Munehiro, c/o Nihon Densan Read K.K.
126, Megawa, Makishimacho
Uji-shi, Kyoto-fu / JP
[2000/30]
Representative(s)Hoffmann Eitle
Patent- und Rechtsanwälte PartmbB
Arabellastrasse 30
81925 München / DE
[N/P]
Former [2000/30]HOFFMANN - EITLE
Patent- und Rechtsanwälte Arabellastrasse 4
81925 München / DE
Application number, filing date00100271.619.01.2000
[2000/30]
Priority number, dateJP1999001116519.01.1999         Original published format: JP 1116599
JP1999035158710.12.1999         Original published format: JP 35158799
[2000/30]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP1022571
Date:26.07.2000
Language:EN
[2000/30]
Type: A3 Search report 
No.:EP1022571
Date:07.11.2001
[2001/45]
Search report(s)(Supplementary) European search report - dispatched on:EP24.09.2001
ClassificationInternational:G01R31/28, G01R31/312
[2001/45]
Former International [2000/30]G01R31/28
Designated contracting statesAT,   BE,   CH,   CY,   DE,   DK,   ES,   FI,   FR,   GB,   GR,   IE,   IT,   LI,   LU,   MC,   NL,   PT,   SE [2000/30]
Extension statesALNot yet paid
LTNot yet paid
LVNot yet paid
MKNot yet paid
RONot yet paid
SINot yet paid
TitleGerman:Vorrichtung und Verfahren zum Prüfen der Leitfähigkeit von Leiterbahnen einer Leiterplatte[2000/30]
English:Apparatus and method for testing electric conductivity of circuit pathways on circuit board[2000/30]
French:Dispositif et méthode de test de la conductivité électrique des pistes d'un circuit[2000/30]
Examination procedure10.01.2002Application withdrawn by applicant  [2002/10]
Documents cited:Search[X]US5517110  (SOIFERMAN JACOB [CA]) [X] 1-18,21-24 * column 5, line 37 - column 6, line 29; figures 1,4 *;
 [X]US5578930  (SHEEN TIMOTHY W [US]) [X] 1,16 * abstract *;
 [PX]WO9965287  (ORBOTECH LTD [IL], et al) [PX] 1,16 * abstract *