Extract from the Register of European Patents

About this file: EP1049162

EP1049162 - Interconnection structure of a multilayer circuit board for electrical connection to a semiconductor package and manufacturing method thereof [Right-click to bookmark this link]
StatusThe application has been withdrawn
Status updated on  16.08.2002
Database last updated on 15.12.2018
Most recent event   Tooltip16.08.2002Withdrawal of applicationpublished on 02.10.2002  [2002/40]
Applicant(s)For all designated states
NEC Corporation
7-1, Shiba 5-chome Minato-ku
Tokyo 108-8001 / JP
[N/P]
Former [2000/44]For all designated states
NEC CORPORATION
7-1, Shiba 5-chome, Minato-ku
Tokyo / JP
Inventor(s)01 / Sakurai, Junya, c/o NEC Corporation
7-1, Shiba 5-chome, Minato-ku
Tokyo / JP
[2000/44]
Representative(s)Betten & Resch
Patent- und Rechtsanwälte PartGmbB
Postfach 10 02 51
80076 München / DE
[N/P]
Former [2000/44]Betten & Resch
Reichenbachstrasse 19
80469 München / DE
Application number, filing date00108979.627.04.2000
[2000/44]
Priority number, dateJP1999011902627.04.1999         Original published format: JP 11902699
[2000/44]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP1049162
Date:02.11.2000
Language:EN
[2000/44]
Type: A3 Search report 
No.:EP1049162
Date:27.06.2001
[2001/26]
Search report(s)(Supplementary) European search report - dispatched on:EP14.05.2001
ClassificationInternational:H01L23/498, H05K1/11, H01L23/538
[2001/26]
Former International [2000/44]H01L23/498
Designated contracting statesDE,   FR [2002/12]
Former [2000/44]AT,  BE,  CH,  CY,  DE,  DK,  ES,  FI,  FR,  GB,  GR,  IE,  IT,  LI,  LU,  MC,  NL,  PT,  SE 
TitleGerman:Verbindungsstruktur einer mehrschichtigen Leiterplatte zur elektrischen Verbindung mit einem Halbleiterbauelement und Verfahren zur Ihrer Herstellung[2000/44]
English:Interconnection structure of a multilayer circuit board for electrical connection to a semiconductor package and manufacturing method thereof[2000/44]
French:Structure d'interconnexions d'une carte de connexion de circuit intégré et procédé pour sa fabrication[2000/44]
Examination procedure05.10.2001Examination requested  [2001/49]
05.08.2002Application withdrawn by applicant  [2002/40]
Fees paidRenewal fee
30.04.2002Renewal fee patent year 03
Documents cited:Search[X]US5858254  (BALZER PETER LYNN [US], et al) [X] 1-28 * column 4, line 1 - column 6, line 9; figures 6,7 *;
 [X]US5612573  (LEWIS ROBERT L [US], et al) [X] 1-28 * column 5, line 45 - column 9, line 8; figures 4-6 *;
 [A]JPH1022643  ;
 [A]JPH10189656  ;
 [A]US5863812  (MANTEGHI KAMRAN [US]) [A] 22,26 * figure 2 *;
 [A]EP0650191  (NEC CORP [JP]) [A] 13,25 * column 6, lines 23-43; figures 5,6 *;
 [A]JPH113915
 [A]  - PATENT ABSTRACTS OF JAPAN, (19980430), vol. 1998, no. 05, [A] 3 * abstract *
 [A]  - PATENT ABSTRACTS OF JAPAN, (19981031), vol. 1998, no. 12, [A] 14,15,24,28 * abstract *
 [A]  - PATENT ABSTRACTS OF JAPAN, (19990430), vol. 1999, no. 04, [A] 23,27 * abstract *