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EP1085517
European procedure
Extract from the Register of European Patents
EP About this file: EP1085517
| EP1085517 - Integrated memory circuit with at least two plate segments [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 11.04.2008 Database last updated on 23.04.2024 | Most recent event Tooltip | 04.07.2008 | Lapse of the patent in a contracting state New state(s): FR | published on 06.08.2008 [2008/32] | Applicant(s) | For all designated states Infineon Technologies AG St.-Martin-Strasse 53 81669 München / DE | [2008/30] |
| Former [2007/23] | For all designated states Infineon Technologies AG St.-Martin-Strasse 53 81669 München / DE | ||
| Former [2001/12] | For all designated states Infineon Technologies AG St.-Martin-Strasse 53 81541 München / DE | Inventor(s) | 01 /
Pöchmüller, Peter Rudolf-Gütlein-Weg 30 81739 München / DE | [2001/12] | Representative(s) | Epping - Hermann - Fischer Patentanwaltsgesellschaft mbH Schlossschmidstrasse 5 80639 München / DE | [N/P] |
| Former [2008/30] | Epping - Hermann - Fischer Patentanwaltsgesellschaft mbH Ridlerstrasse 55 80339 München / DE | ||
| Former [2004/04] | Epping, Hermann, Fischer Patentanwaltsgesellschaft mbH Ridlerstrasse 55 80339 München / DE | ||
| Former [2001/12] | Fischer, Volker, Dipl.-Ing., et al Epping Hermann & Fischer Ridlerstrasse 55 80339 München / DE | Application number, filing date | 00119661.7 | 08.09.2000 | [2001/12] | Priority number, date | DE1999144036 | 14.09.1999 Original published format: DE 19944036 | [2001/12] | Filing language | DE | Procedural language | DE | Publication | Type: | A2 Application without search report | No.: | EP1085517 | Date: | 21.03.2001 | Language: | DE | [2001/12] | Type: | A3 Search report | No.: | EP1085517 | Date: | 28.03.2001 | [2001/13] | Type: | B1 Patent specification | No.: | EP1085517 | Date: | 06.06.2007 | Language: | DE | [2007/23] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 09.02.2001 | Classification | IPC: | G11C11/407, G11C11/22, G11C29/00 | [2001/13] | CPC: |
G11C11/22 (EP,KR,US);
G11C11/4074 (EP,US)
|
| Former IPC [2001/12] | G11C11/404 | Designated contracting states | DE, FR, GB, IE, IT [2001/51] |
| Former [2001/12] | AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE | Title | German: | Integrierter Speicher mit wenigstens zwei Plattensegmenten | [2001/12] | English: | Integrated memory circuit with at least two plate segments | [2001/12] | French: | Circuit mémoire intégré avec au moins deux segments de plaque | [2001/12] | Examination procedure | 26.09.2001 | Examination requested [2001/47] | 15.12.2006 | Communication of intention to grant the patent | 12.04.2007 | Fee for grant paid | 12.04.2007 | Fee for publishing/printing paid | Opposition(s) | 07.03.2008 | No opposition filed within time limit [2008/20] | Fees paid | Renewal fee | 23.09.2002 | Renewal fee patent year 03 | 24.09.2003 | Renewal fee patent year 04 | 23.09.2004 | Renewal fee patent year 05 | 21.09.2005 | Renewal fee patent year 06 | 28.09.2006 | Renewal fee patent year 07 |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | GB | 06.06.2007 | IE | 06.06.2007 | IT | 06.06.2007 | FR | 01.02.2008 | [2008/32] |
| Former [2008/23] | GB | 06.06.2007 | |
| IE | 06.06.2007 | ||
| IT | 06.06.2007 | ||
| Former [2008/19] | GB | 06.06.2007 | |
| IE | 06.06.2007 | ||
| Former [2008/10] | IE | 06.06.2007 | Documents cited: | Search | [A]US5400275 (ABE KAZUHIDE [JP], et al) [A] 1* column 38, line 27 - column 39, line 4; figure 49 * |