Extract from the Register of European Patents

About this file: EP1050820

EP1050820 - A semiconductor memory device with a large storage capacity memory and a fast speed memory [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  26.05.2006
Database last updated on 17.11.2017
Most recent event   Tooltip26.05.2006Application deemed to be withdrawnpublished on 28.06.2006  [2006/26]
Applicant(s)For all designated states
MITSUBISHI DENKI KABUSHIKI KAISHA
7-3, Marunouchi 2-chome Chiyoda-ku
Tokyo 100-8310 / JP
[2006/18]
Former [2000/45]For all designated states
MITSUBISHI DENKI KABUSHIKI KAISHA
2-3, Marunouchi 2-chome Chiyoda-ku
Tokyo / JP
Inventor(s)01 / Konishi, Yasuhiro, c/o Mitsubishi Denki K.K.
LSI Kenkyusho, 1 Mizuhara 4-chome
Itami-shi, Hyogo-ken / JP
02 / Dosaka, Katsumi, c/o Mitsubishi Denki K.K.
LSI Kenkyusho, 1 Mizuhara 4-chome
Itami-shi, Hyogo-ken / JP
03 / Hayano, Kouji, c/o Mitsubishi Denki K.K.
Kitaitami Seisakusho, 1 Mizuhara 4-chome
Itami-shi, Hyogo-ken / JP
04 / Kumanoya, Masaki, c/o Mitsubishi Denki K.K.
LSI Kenkyusho, 1 Mizuhara 4-chome
Itami-shi, Hyogo-ken / JP
05 / Yamazaki, Akira, c/o Mitsubishi Denki K.K.
LSI Kenkyusho, 1 Mizuhara 4-chome
Itami-shi, Hyogo-ken / JP
06 / Iwamoto, Hisashi, c/o Mitsubishi Denki K.K.
LSI Kenkyusho, 1 Mizuhara 4-chome
Itami-shi, Hyogo-ken / JP
[2000/45]
Representative(s)Beresford, Keith Denis Lewis , et al
Beresford Crump LLP
16 High Holborn
London WC1V 6BX / GB
[N/P]
Former [2000/45]Beresford, Keith Denis Lewis , et al
BERESFORD & Co. High Holborn 2-5 Warwick Court
London WC1R 5DJ / GB
Application number, filing date00202043.627.09.1991
[2000/45]
Priority number, dateJP1990040604025.12.1990         Original published format: JP 40604090
JP1991001767708.02.1991         Original published format: JP 1767791
JP1991008424816.04.1991         Original published format: JP 8424891
[2000/45]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP1050820
Date:08.11.2000
Language:EN
[2000/45]
Type: A3 Search report 
No.:EP1050820
Date:06.06.2001
[2001/23]
Search report(s)(Supplementary) European search report -
dispatched on:
EP25.04.2001
ClassificationInternational:G06F12/08, G11C7/00, G11C11/00
[2001/23]
Former International [2000/45]G06F12/08, G11C7/00
Designated contracting statesDE,   FR,   GB,   IT [2000/45]
TitleGerman:Halbleiterspeichervorrichtung mit einem grossen Speicher und einem Hochgeschwindigkeitsspeicher[2000/45]
English:A semiconductor memory device with a large storage capacity memory and a fast speed memory[2000/45]
French:Dispositif de mémoire semi-conductrice avec une mémoire à grande capacité et une mémoire à grande vitesse[2000/45]
Examination procedure01.06.2001Examination requested  [2001/31]
22.07.2002Despatch of a communication from the examining division (Time limit: M04)
25.11.2002Reply to a communication from the examining division
15.07.2005Despatch of a communication from the examining division (Time limit: M04)
25.11.2005Application deemed to be withdrawn, date of legal effect  [2006/26]
16.01.2006Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time  [2006/26]
Parent application(s)   TooltipEP91308902.5  / EP0492776
EP97202423.6  / EP0811979
Divisional application(s)EP02080048.8  / EP1293906
Fees paidRenewal fee
06.07.2000Renewal fee patent year 03
06.07.2000Renewal fee patent year 04
06.07.2000Renewal fee patent year 05
06.07.2000Renewal fee patent year 06
06.07.2000Renewal fee patent year 07
06.07.2000Renewal fee patent year 08
06.07.2000Renewal fee patent year 09
25.09.2000Renewal fee patent year 10
24.09.2001Renewal fee patent year 11
25.09.2002Renewal fee patent year 12
19.09.2003Renewal fee patent year 13
20.09.2004Renewal fee patent year 14
Penalty fee
Additional fee for renewal fee
30.09.200515   M06   Not yet paid
Documents cited:Search[E]DE4110173  (MITSUBISHI ELECTRIC CORP [JP]) [E] 1-6,8-21 * column 3, line 23 - column 4, line 12; figure 2 *;
 [XY]  HIDETO HIDAKA ET AL, "THE CACHE DRAM ARCHITECTURE: A DRAM WITH AN ON-CHIP CACHE MEMORY", IEEE MICRO,US,IEEE INC. NEW YORK, (19900401), vol. 10, no. 2, ISSN 0272-1732, pages 14 - 25, XP000116649 [X] 1,3-6,8-21 * page 18, column R, paragraph L - page 19, column L, paragraph 3; figure 4 * [Y] 2
 [YA]  ARIMOTO K ET AL, A CIRCUIT DESIGN OF INTELLIGENT CDRAM WITH AUTOMATIC WRITE BACK CAPABILITY, SYMPOSIUM ON VLSI CIRCUITS,US,NEW YORK, IEEE, VOL. SYMP. 4, PAGE(S) 79-80, XP000145616 [Y] 2 * the whole document * [A] 1,3-21