Extract from the Register of European Patents

About this file: EP1241678

EP1241678 - Built-in self test circuit employing a linear feedback shift register [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  27.10.2006
Database last updated on 24.04.2019
Most recent event   Tooltip27.10.2006No opposition filed within time limitpublished on 29.11.2006  [2006/48]
Applicant(s)For all designated states
Samsung Electronics Co., Ltd.
416, Maetan-dong
Paldal-gu
Suwon-City, Kyungki-do / KR
[N/P]
Former [2005/51]For all designated states
SAMSUNG ELECTRONICS CO., LTD.
416, Maetan-dong, Paldal-gu Suwon-City
Kyungki-do / KR
Former [2002/38]For all designated states
SAMSUNG ELECTRONICS CO., LTD.
416, Maetan-dong, Paldal-gu
Suwon-City, Kyungki-do / KR
Inventor(s)01 / Kim, Heon-Cheol
302, 278-6, Yangjae-dong, Seocho-ku
Seoul / KR
02 / Park, Jin-Young
7-1, Nongseo-ri, Kiheung-eub
Yongin-shi, Kyunggi-do / KR
 [2002/38]
Representative(s)Mounteney, Simon James
Marks & Clerk LLP
15 Fetter Lane
London EC4A 1BW / GB
[N/P]
Former [2002/38]Mounteney, Simon James
MARKS & CLERK, 57-60 Lincoln's Inn Fields
London WC2A 3LS / GB
Application number, filing date01305658.529.06.2001
[2002/38]
Priority number, dateUS2001080543113.03.2001         Original published format: US 805431
[2002/38]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP1241678
Date:18.09.2002
Language:EN
[2002/38]
Type: A3 Search report 
No.:EP1241678
Date:03.09.2003
[2003/36]
Type: B1 Patent specification 
No.:EP1241678
Date:21.12.2005
Language:EN
[2005/51]
Search report(s)(Supplementary) European search report - dispatched on:EP23.07.2003
ClassificationInternational:G11C29/00
[2002/38]
Designated contracting statesDE,   FR,   GB,   NL [2004/22]
Former [2002/38]AT,  BE,  CH,  CY,  DE,  DK,  ES,  FI,  FR,  GB,  GR,  IE,  IT,  LI,  LU,  MC,  NL,  PT,  SE,  TR 
TitleGerman:Eingebaute Selbsttestschaltung mit einem Schieberegister mit linearer Rückkopplung[2002/38]
English:Built-in self test circuit employing a linear feedback shift register[2002/38]
French:Circuit d'auto-test intégré employant un registre à décalage à rebouclage linéaire[2002/38]
Examination procedure11.07.2001Examination requested  [2002/38]
23.08.2004Despatch of a communication from the examining division (Time limit: M04)
13.12.2004Reply to a communication from the examining division
17.06.2005Communication of intention to grant the patent
19.10.2005Fee for grant paid
19.10.2005Fee for publishing/printing paid
Opposition(s)22.09.2006No opposition filed within time limit [2006/48]
Fees paidRenewal fee
28.08.2003Renewal fee patent year 03
28.06.2004Renewal fee patent year 04
14.06.2005Renewal fee patent year 05
Penalty fee
Additional fee for renewal fee
30.06.200303   M06   Fee paid on   28.08.2003
Documents cited:Search[Y]US6006345  (BERRY JR ROBERT W [US]) [Y] 1,10 * column 3, line 5 - line 23; figure 1B * * column 3, line 46 - column 4, line 4; figure 2 *;
 [Y]US5033048  (PIERCE DONALD C [US], et al) [Y] 1,10 * abstract *;
 [DA]US5706293  (KIM HEON-CHEOL [KR], et al) [DA] 1-13 * the whole document *;
 [A]US5258986  (ZERBE JARED L [US]) [A] 1-13 * column 3, line 38 - column 5, line 30; figures 6-13 *