Extract from the Register of European Patents

About this file: EP1321984

EP1321984 - Semiconductor input/output circuit arrangement [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  21.08.2009
Database last updated on 12.11.2018
Most recent event   Tooltip21.08.2009Application deemed to be withdrawnpublished on 23.09.2009  [2009/39]
Applicant(s)For all designated states
STMicroelectronics Limited
1000 Aztec West Almondsbury
Bristol BS32 4SQ / GB
[N/P]
Former [2003/26]For all designated states
STMicroelectronics Limited
1000 Aztec West
Almondsbury, Bristol BS32 4SQ / GB
Inventor(s)01 / Thies, William
2 Bramley Close, Olveston
Bristol BS35 4EA / GB
02 / Froidevaux, Nicolas
8 Rue Peyresc
13100 Aix en Provence / FR
 [2003/26]
Representative(s)Loveless, Ian Mark
Reddie & Grose LLP The White Chapel Building
10 Whitechapel High Street
London E1 8QS / GB
[N/P]
Former [2003/26]Loveless, Ian Mark
Reddie & Grose, 16 Theobalds Road
London WC1X 8PL / GB
Application number, filing date01307231.924.08.2001
[2003/26]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP1321984
Date:25.06.2003
Language:EN
[2003/26]
Type: A3 Search report 
No.:EP1321984
Date:14.01.2004
[2004/03]
Search report(s)(Supplementary) European search report - dispatched on:EP27.11.2003
ClassificationInternational:H01L27/118, H01L27/02, H01L23/528
[2003/26]
Designated contracting statesDE,   FR,   GB,   IT [2004/41]
Former [2003/26]AT,  BE,  CH,  CY,  DE,  DK,  ES,  FI,  FR,  GB,  GR,  IE,  IT,  LI,  LU,  MC,  NL,  PT,  SE,  TR 
TitleGerman:Eingangs/Ausgangs-Schaltungsanordnung für einen integrierten Halbleiterbaustein[2003/26]
English:Semiconductor input/output circuit arrangement[2003/26]
French:Système de circuit d'entrée/sortie dans un circuit intégré à semi-conducteur[2003/26]
Examination procedure08.07.2004Examination requested  [2004/37]
03.03.2009Application deemed to be withdrawn, date of legal effect  [2009/39]
09.04.2009Despatch of communication that the application is deemed to be withdrawn, reason: renewal fee not paid in time  [2009/39]
Fees paidRenewal fee
13.08.2003Renewal fee patent year 03
12.08.2004Renewal fee patent year 04
12.08.2005Renewal fee patent year 05
14.08.2006Renewal fee patent year 06
28.08.2007Renewal fee patent year 07
Penalty fee
Additional fee for renewal fee
31.08.200808   M06   Not yet paid
Documents cited:Search[X]EP0563973  (NEC CORP [JP]) [X] 1,5,12,13,18 * figures 1,2 * * claims 1,3 * * column 1, line 13 - line 33 * * column 3, line 49 - column 5, line 41 *;
 [X]US5777354  (CHEUNG GARY H [US], et al) [X] 1,3,5,7,12,13,18 * column 1, line 23 - line 30 * * column 3, line 17 - line 35 * * column 5, line 34 - line 49 * * claims 5-10 *;
 [X]JP2000208706  (ROHM CO LTD) [X] 9-11;
 []US6362497  (HIRAGA NONAKI [JP]) [ ] * column 1, line 13 - column 6, line 8 * * claims 1,2,6,7,12 * * figures 1,5-8 *;
 [XY]EP0660410  (TEXAS INSTRUMENTS INC [US], et al) [X] 14-17 * the whole document * [Y] 1-8,12,13,18;
 [YA]US6078068  (TAMURA RONALD KAZUO [US]) [Y] 1-8,12,13,18 * column 1, line 11 - column 6, line 4 * * claims 1,11,17,18 * * figures 1,2 * [A] 9;
 [A]US5760428  (COLWELL MICHAEL J [US], et al) [A] 1-14,17,18 * column 5, line 8 - column 7, line 41 * * figures 1A,2A *;
 [A]US6130484  (KAMEDA HIDEO [JP], et al) [A] 1,5,9,12-16,18 * column 1, line 42 - column 3, line 3 * * column 4, line 64 - column 5, line 35 * * claims 1,3,5 * * figures 1,4-9 *;
 [A]US5548135  (AVERY LESLIE R [US]) [A] 9,11 * the whole document *;
 [A]US5365091  (YAMAGISHI MIKIO [JP]) [A] 14-16 * column 1, line 7 - column 8, line 46 * * claims 1,3-10,13-16 * * figures 1-3 *;
 [T]  MACK W D ET AL, New ESD protection schemes for BiCMOS processes with application to cellular radio designs, PROCEEDINGS OF THE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS. SAN DIEGO, MAY 10 - 13, 1992, PROCEEDINGS OF THE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS. (ISCAS), NEW YORK, IEEE, US, VOL. VOL. 4 CONF. 25, PAGE(S) 2699-2702, ISBN 0-7803-0593-0, XP010061733

DOI:   http://dx.doi.org/10.1109/ISCAS.1992.230663
 [T]  WORLEY E R ET AL, "Sub-micron chip ESD protection schemes which avoid avalanching junctions", DATABASE INSPEC, INSTITUTE OF ELECTRICAL ENGINEERS, STEVENAGE, GB, Database accession no. 5255413, XP002260510 [T] * abstract *
    [] ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS (IEEE CAT. NO.95TH8088), PROCEEDINGS OF 17TH ANNUAL ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM, PHOENIX, AZ, USA, 12-14 SEPT. 1995, 1995, Rome, NY, USA, ESD Assoc, USA, pages 13 - 20,