Extract from the Register of European Patents

About this file: EP1162741

EP1162741 - Adiabatic charging register circuit [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  22.05.2009
Database last updated on 15.01.2019
Most recent event   Tooltip22.05.2009No opposition filed within time limitpublished on 24.06.2009  [2009/26]
Applicant(s)For all designated states
NIPPON TELEGRAPH AND TELEPHONE CORPORATION
3-1, Otemachi 2-chome, Chiyoda-ku
Tokyo 100-8116 / JP
[2008/29]
Former [2001/50]For all designated states
Nippon Telegraph and Telephone Corporation
3-1, Otemachi 2-chome, Chiyoda-ku
Tokyo 100-8116 / JP
Inventor(s)01 / Nakata, Shunji, c/o NTT Intellectual Prop. Center
9-11, Midori-cho 3-chome
Musashino-shi, Tokyo 180-8585 / JP
02 / Kado, Yuuichi, c/o NTT Intellectual Prop. Center
9-11, Midori-cho 3-chome
Musashino-shi, Tokyo 180-8585 / JP
 [2001/50]
Representative(s)de Beaumont, Michel
Cabinet Michel de Beaumont
1, rue Champollion
38000 Grenoble / FR
[N/P]
Former [2001/50]de Beaumont, Michel
Cabinet Michel de Beaumont 1, rue Champollion
38000 Grenoble / FR
Application number, filing date01410063.005.06.2001
[2001/50]
Priority number, dateJP2000016884606.06.2000         Original published format: JP 2000168846
[2001/50]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP1162741
Date:12.12.2001
Language:EN
[2001/50]
Type: A3 Search report 
No.:EP1162741
Date:23.03.2005
[2005/12]
Type: B1 Patent specification 
No.:EP1162741
Date:16.07.2008
Language:EN
[2008/29]
Search report(s)(Supplementary) European search report - dispatched on:EP04.02.2005
ClassificationInternational:H03K3/012
[2001/50]
Designated contracting statesDE,   FR,   GB,   IT [2005/50]
Former [2001/50]AT,  BE,  CH,  CY,  DE,  DK,  ES,  FI,  FR,  GB,  GR,  IE,  IT,  LI,  LU,  MC,  NL,  PT,  SE,  TR 
TitleGerman:Registerschaltung mit adiabatischer Ladung[2001/50]
English:Adiabatic charging register circuit[2001/50]
French:Circuit de régistre à charge adiabatique[2001/50]
Examination procedure20.07.2005Examination requested  [2005/50]
03.07.2007Despatch of a communication from the examining division (Time limit: M06)
03.01.2008Reply to a communication from the examining division
11.02.2008Communication of intention to grant the patent
22.05.2008Fee for grant paid
22.05.2008Fee for publishing/printing paid
Opposition(s)17.04.2009No opposition filed within time limit [2009/26]
Fees paidRenewal fee
20.06.2003Renewal fee patent year 03
19.06.2004Renewal fee patent year 04
20.06.2005Renewal fee patent year 05
20.06.2006Renewal fee patent year 06
15.06.2007Renewal fee patent year 07
17.03.2008Renewal fee patent year 08
Documents cited:Search[A]US5936455  (KOBAYASHI SOUICHI [JP], et al) [A] 1-5 * column 5, line 8 - column 6, line 21 * * column 21, line 58 - column 23, line 15 * * figures 3,4,32-34 *;
 [A]EP0901230  (NIPPON TELEGRAPH & TELEPHONE [JP]) [A] 1-5 * paragraph [0034] - paragraph [0040]; figures 7-10 *;
 [A]EP0851323  (SEIKO EPSON CORP [JP]) [A] 1-5 * column 6, line 43 - column 9; figures 1-5 *
 [A]  KIM J-C ET AL, "A LOW-POWER HALF-SWING CLOCKING SCHEME FOR FLIP-FLOP WITH COMPLEMENTARY GATE AND SOURCE DRIVE", IEICE TRANSACTIONS ON ELECTRONICS, INSTITUTE OF ELECTRONICS INFORMATION AND COMM. ENG. TOKYO, JP, (199909), vol. E82-C, no. 9, ISSN 0916-8524, pages 1777 - 1779, XP000930743 [A] 1-5 * page 1777, column L, paragraph L - page 1779, column L, paragraph L; figures 1-4 *
by applicant   JIN-CHEON KIM ET AL., "A Low-Power Half-Swing Cloking Scheme for Flip-flop with Complementary Gate and Source Drive", IEICE TRANS.ELECTRON, (199909),