Extract from the Register of European Patents

About this file: EP1257130

EP1257130 - System and method for optimizing state machine transitional performance [Right-click to bookmark this link]
Former [2002/46]State machine architecture partitionable into control and data planes
[2005/33]
StatusThe application is deemed to be withdrawn
Status updated on  02.06.2006
Database last updated on 18.01.2019
Most recent event   Tooltip02.06.2006Application deemed to be withdrawnpublished on 05.07.2006  [2006/27]
Applicant(s)For all designated states
ALCATEL
54, rue La Boétie
75008 Paris / FR
[2002/46]
Inventor(s)01 / Gammenthaler, Robert S., Jr.
4729 Logan Court
Frisco, TX 75035 / US
 [2002/46]
Representative(s)Rausch, Gabriele
Alcatel Intellectual Property Department Stuttgart
70430 Stuttgart / DE
[N/P]
Former [2005/45]Rausch, Gabriele
Alcatel Intellectual Property Department, Stuttgart
70430 Stuttgart / DE
Former [2002/46]Dreiss, Fuhlendorf, Steimle & Becker
Patentanwälte, Postfach 10 37 62
70032 Stuttgart / DE
Application number, filing date02008440.613.04.2002
[2002/46]
Priority number, dateUS2001085338711.05.2001         Original published format: US 853387
[2002/46]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP1257130
Date:13.11.2002
Language:EN
[2002/46]
Type: A3 Search report 
No.:EP1257130
Date:28.01.2004
[2004/05]
Search report(s)(Supplementary) European search report - dispatched on:EP12.12.2003
ClassificationInternational:H04Q3/00
[2002/46]
Designated contracting statesAT,   BE,   CH,   CY,   DE,   DK,   ES,   FI,   FR,   GB,   GR,   IE,   IT,   LI,   LU,   MC,   NL,   PT,   SE,   TR [2002/46]
TitleGerman:System un Verfahren zur Übergangsoptimisierung von einem Automat[2005/33]
English:System and method for optimizing state machine transitional performance[2005/33]
French:Système et méthode pour optimiser les performances transitoires d'un machine à états[2005/33]
Former [2002/46]Automat-Architektur, diein eine Steuerungsebene und eine Datenebene unterteilbar ist
Former [2002/46]State machine architecture partitionable into control and data planes
Former [2002/46]Architecture de machine à états, qui peut être divisé en un plan de contrôle et un un plan de données
Examination procedure28.07.2004Examination requested  [2004/40]
31.07.2004Amendment by applicant (claims and/or description)
03.11.2004Despatch of a communication from the examining division (Time limit: M06)
27.04.2005Reply to a communication from the examining division
18.08.2005Communication of intention to grant the patent
29.12.2005Application deemed to be withdrawn, date of legal effect  [2006/27]
03.02.2006Despatch of communication that the application is deemed to be withdrawn, reason: fee for grant / fee for printing not paid in time  [2006/27]
Fees paidRenewal fee
14.04.2004Renewal fee patent year 03
11.04.2005Renewal fee patent year 04
Penalty fee
Additional fee for renewal fee
30.04.200605   M06   Not yet paid
Documents cited:Search[A]US5987035  (SILVA MICHAEL [US]) [A] 1-20 * column A * * column 1, line 41 - column 2, line 17 * * column 4, line 48 - line 67 * * figure 3 *;
 [A]US5546453  (HEBERT MARK P [US]) [A] 1-20 * column A * * column 1, line 38 - line 42 * * column 2, line 34 - line 54 *