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EP1484795
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EP About this file: EP1484795
| EP1484795 - Method for manufacturing a chip scale package at wafer level [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 14.05.2010 Database last updated on 26.03.2025 | Most recent event Tooltip | 14.05.2010 | Application deemed to be withdrawn | published on 16.06.2010 [2010/24] | Applicant(s) | For all designated states NORTHROP GRUMMAN CORPORATION 1840 Century Park East Century City Los Angeles, California 90067-2199 / US | [N/P] |
| Former [2004/50] | For all designated states NORTHROP GRUMMAN CORPORATION 1840 Century Park East Century City Los Angeles California 90067-2199 / US | Inventor(s) | 01 /
Anderson, James 5778 Woodboro Drive Huntington Beach CA 92649 / US | 02 /
Akerling, Gershon 5430 Diller Street Culver city CA 90230 / US | [2004/50] | Representative(s) | Schmidt, Steffen J. Wuesthoff & Wuesthoff Patentanwälte und Rechtsanwalt PartG mbB Schweigerstrasse 2 81541 München / DE | [N/P] |
| Former [2004/50] | Schmidt, Steffen J., Dipl.-Ing. Wuesthoff & Wuesthoff, Patent- und Rechtsanwälte, Schweigerstrasse 2 81541 München / DE | Application number, filing date | 03026821.3 | 20.11.2003 | [2004/50] | Priority number, date | US20030454081 | 04.06.2003 Original published format: US 454081 | [2004/50] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP1484795 | Date: | 08.12.2004 | Language: | EN | [2004/50] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 03.06.2004 | Classification | IPC: | H01L23/31, H01L23/48 | [2004/50] | CPC: |
H01L24/49 (EP,US);
H01L23/3114 (EP,US);
H01L23/481 (EP,US);
H01L23/482 (EP,US);
H01L23/5286 (EP,US);
H01L25/105 (EP,US);
H01L2224/32245 (EP,US);
H01L2224/48091 (EP,US);
H01L2224/48247 (EP,US);
H01L2224/48257 (EP,US);
H01L2224/48465 (EP,US);
H01L2224/4911 (EP,US);
H01L2224/73265 (EP,US);
H01L2225/1035 (EP,US);
H01L2225/1058 (EP,US);
H01L24/48 (EP,US);
H01L2924/00014 (EP,US);
H01L2924/01004 (EP,US);
H01L2924/01006 (EP,US);
H01L2924/01014 (EP,US);
H01L2924/01029 (EP,US);
H01L2924/01074 (EP,US);
H01L2924/01075 (EP,US);
H01L2924/014 (EP,US);
H01L2924/10329 (EP,US);
H01L2924/14 (EP,US);
H01L2924/15313 (EP,US);
| C-Set: |
H01L2224/48091, H01L2924/00014 (US,EP);
H01L2224/48465, H01L2224/48091, H01L2924/00 (EP,US);
H01L2224/48465, H01L2224/48247, H01L2924/00 (US,EP);
H01L2224/4911, H01L2224/48247, H01L2924/19107 (US,EP);
H01L2224/73265, H01L2224/32245, H01L2224/48247, H01L2924/00015 (EP,US);
H01L2224/73265, H01L2224/32245, H01L2224/48257, H01L2924/00015 (US,EP);
H01L2924/00014, H01L2224/05599 (EP,US);
H01L2924/00014, H01L2224/45099 (EP,US); | Designated contracting states | DE, FR, GB [2005/35] |
| Former [2004/50] | AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LI, LU, MC, NL, PT, RO, SE, SI, SK, TR | Title | German: | Verfahren zur Herstellung auf Wafer-Ebene eines Gehäuses auf Chip-Massstab | [2004/50] | English: | Method for manufacturing a chip scale package at wafer level | [2004/50] | French: | Procédé de formation d'un boîtier à puce au niveau de la plaquette | [2004/50] | Examination procedure | 07.04.2005 | Examination requested [2005/23] | 12.05.2005 | Despatch of a communication from the examining division (Time limit: M04) | 21.06.2005 | Loss of particular rights, legal effect: designated state(s) | 23.08.2005 | Reply to a communication from the examining division | 27.09.2005 | Despatch of communication of loss of particular rights: designated state(s) AT, BE, BG, CH, CY, CZ, DK, EE, ES, FI, GR, HU, IE, IT, LU, MC, NL, PT, RO, SE, SI, SK, TR | 13.03.2007 | Despatch of a communication from the examining division (Time limit: M06) | 12.09.2007 | Reply to a communication from the examining division | 12.08.2009 | Despatch of a communication from the examining division (Time limit: M04) | 23.12.2009 | Application deemed to be withdrawn, date of legal effect [2010/24] | 26.01.2010 | Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time [2010/24] | Fees paid | Renewal fee | 29.11.2005 | Renewal fee patent year 03 | 27.11.2006 | Renewal fee patent year 04 | 27.11.2007 | Renewal fee patent year 05 | 17.11.2008 | Renewal fee patent year 06 | Penalty fee | Penalty fee Rule 85a EPC 1973 | 13.07.2005 | AT M01 Not yet paid | 13.07.2005 | BE M01 Not yet paid | 13.07.2005 | BG M01 Not yet paid | 13.07.2005 | CH M01 Not yet paid | 13.07.2005 | CY M01 Not yet paid | 13.07.2005 | CZ M01 Not yet paid | 13.07.2005 | DK M01 Not yet paid | 13.07.2005 | EE M01 Not yet paid | 13.07.2005 | ES M01 Not yet paid | 13.07.2005 | FI M01 Not yet paid | 13.07.2005 | GR M01 Not yet paid | 13.07.2005 | HU M01 Not yet paid | 13.07.2005 | IE M01 Not yet paid | 13.07.2005 | IT M01 Not yet paid | 13.07.2005 | LU M01 Not yet paid | 13.07.2005 | MC M01 Not yet paid | 13.07.2005 | NL M01 Not yet paid | 13.07.2005 | PT M01 Not yet paid | 13.07.2005 | RO M01 Not yet paid | 13.07.2005 | SE M01 Not yet paid | 13.07.2005 | SI M01 Not yet paid | 13.07.2005 | SK M01 Not yet paid | 13.07.2005 | TR M01 Not yet paid | Additional fee for renewal fee | 30.11.2009 | 07 M06 Not yet paid |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]EP1085569 (VISHAY INTERTECHNOLOGY INC [US]) [A] 1 * paragraph [0018] - paragraph [0044]; figures 1-13 *; | [A]US2001005043 (NAKANISHI MASAKI [JP], et al) [A] 1* paragraph [0086] - paragraph [0099]; figures 5-9 *; | [X]US2003080398 (BADEHI AVNER [IL]) [X] 1-10 * paragraph [0061] - paragraph [0087]; figures 1-6 * |