Extract from the Register of European Patents

About this file: EP1560376

EP1560376 - System-on-chip establishing paths between routers and method therefor [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  11.12.2009
Database last updated on 22.02.2019
Most recent event   Tooltip11.12.2009No opposition filed within time limitpublished on 13.01.2010  [2010/02]
Applicant(s)For all designated states
Samsung Electronics Co., Ltd.
416 Maetan dong
Yeongtong-gu
Suwon-city
Gyeonggi-do / KR
[N/P]
Former [2009/06]For all designated states
SAMSUNG ELECTRONICS CO., LTD.
416 Maetan dong, Yeongtong-gu Suwon-city
Gyeonggi-do / KR
Former [2005/31]For all designated states
Samsung Electronics Co., Ltd.
416 Maetan dong, Yeongtong-gu
Suwon-city, Gyeonggi-do / KR
Inventor(s)01 / Rhim, Sang-woo
101-1003, doosan Weve Apt. 252-1 Nonhyeon-dong
Gangnam-gu Seoul / KR
02 / Lee, Jae-kon
108-808, Dongswon LG Village Mangpo-dong
Paldal-gu Suwon-si Gyeonggi-do / KR
03 / Lee, Beam-hak
150-2, Seokchon-dong Songpa-gu
Seoul / KR
04 / Kim, Eui-seok
207-701, Samsung Apt Yuljeon-dong
Jangan-gu Suwon-si Gyeonggi-do / KR
 [2009/06]
Former [2005/31]01 / Rhim, Sang-Woo
101-1003, doosan Weve Apt. 252-1 Nonhyeon-dong
Gangnam-gu Seoul / KR
02 / Lee, Jae-Kon
108-808, Dongswon LG Village Mangpo-dong
Paldal-gu Suwon-si Gyeonggi-do / KR
03 / Lee, Beam-hak
150-2, Seokchon-dong Songpa-gu
Seoul / KR
04 / Kim, Eui-seok
207-701, Samsung Apt Yuljeon-dong
Jangan-gu Suwon-si Gyeonggi-do / KR
Representative(s)Anderson, James Edward George
Elkington and Fife LLP
Prospect House
8 Pembroke Road
Sevenoaks, Kent TN13 1XR / GB
[N/P]
Former [2007/18]Anderson, James Edward George
Elkington and Fife LLP Prospect House 8 Pembroke Road
Sevenoaks, Kent TN13 1XR / GB
Former [2005/31]Ertl, Nicholas Justin
Elkington and Fife LLP, Prospect House, 8 Pembroke Road
Sevenoaks, Kent TN13 1XR / GB
Application number, filing date04257650.409.12.2004
[2005/31]
Priority number, dateKR2004000532828.01.2004         Original published format: KR 2004005328
[2005/31]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP1560376
Date:03.08.2005
Language:EN
[2005/31]
Type: B1 Patent specification 
No.:EP1560376
Date:04.02.2009
Language:EN
[2009/06]
Search report(s)(Supplementary) European search report - dispatched on:EP06.05.2005
ClassificationInternational:H04L12/56, G06F15/16
[2005/31]
Designated contracting statesFI,   FR,   GB,   SE [2006/17]
Former [2005/31]AT,  BE,  BG,  CH,  CY,  CZ,  DE,  DK,  EE,  ES,  FI,  FR,  GB,  GR,  HU,  IE,  IS,  IT,  LI,  LT,  LU,  MC,  NL,  PL,  PT,  RO,  SE,  SI,  SK,  TR 
TitleGerman:System-on-chip zum Pfadaufbau zwischen Routern und Verfahren dazu[2005/31]
English:System-on-chip establishing paths between routers and method therefor[2005/31]
French:System-on-chip pour l'établissement de chemins entre routeurs et procédé à cet effet[2008/23]
Former [2005/31]System-on-chip pour l'établissement de chemins entre routers procédé à cet effet
Examination procedure21.09.2005Examination requested  [2005/46]
05.01.2006Despatch of a communication from the examining division (Time limit: M04)
04.02.2006Loss of particular rights, legal effect: designated state(s)
02.05.2006Reply to a communication from the examining division
12.02.2007Despatch of a communication from the examining division (Time limit: M04)
01.06.2007Reply to a communication from the examining division
13.06.2007Despatch of communication of loss of particular rights: designated state(s) DE
14.02.2008Despatch of a communication from the examining division (Time limit: M02)
23.04.2008Reply to a communication from the examining division
14.05.2008Communication of intention to grant the patent
24.09.2008Fee for grant paid
24.09.2008Fee for publishing/printing paid
Opposition(s)05.11.2009No opposition filed within time limit [2010/02]
Fees paidRenewal fee
01.11.2006Renewal fee patent year 03
24.10.2007Renewal fee patent year 04
17.12.2008Renewal fee patent year 05
Penalty fee
Penalty fee Rule 85a EPC 1973
26.03.2007DE   M01   Not yet paid
Lapses during opposition  TooltipFI04.02.2009
SE04.05.2009
[2009/40]
Documents cited:Search[X]  SATHE S ET AL, "Design of a switching node (router) for on-chip networks", ASIC, 2003. PROCEEDINGS. 5TH INTERNATIONAL CONFERENCE ON OCT. 21-24, 2003, PISCATAWAY, NJ, USA,IEEE, (20031021), vol. 1, ISBN 0-7803-7889-X, pages 75 - 78, XP010690634 [X] 1-31 * abstract * * paragraph [04.3] * * figure 1 *

DOI:   http://dx.doi.org/10.1109/ICASIC.2003.1277494
 [A]  BARTIC T A ET AL, "Highly scalable network on chip for reconfigurable systems", SYSTEM-ON-CHIP, 2003. PROCEEDINGS. INTERNATIONAL SYMPOSIUM ON NOV. 19-21, 2003, PISCATAWAY, NJ, USA,IEEE, (20031119), ISBN 0-7803-8160-2, pages 79 - 82, XP010682717 [A] 1-31 * the whole document *

DOI:   http://dx.doi.org/10.1109/ISSOC.2003.1267722
 [A]  SAASTAMOINEN ET AL, "Interconnect IP Node for Future System-on-Chip Designs", PROCEEDINGS OF THE IEEE INTERNATIONAL WORKSHOP ON ELECTRONIC DESIGN, TEST AND APPLICATIONS, (200201), pages 1 - 5, XP002272946 [A] 1-31 * the whole document *
 [A]  RIJPKEMA E ET AL, "A Router Architecture for Networks on Silicon", PROGRESS. WORKSHOP ON EMBEDDED SYSTEMS, (200111), pages 181 - 188, XP002280718 [A] 1-31 * the whole document *
 [A]  KUMAR S ET AL, "A Network on Chip Architecture and Design Methodology", VLSI ON ANNUAL SYMPOSIUM, IEEE COMPUTER SOCIETY ISVLSI 2002 PITTSBURGH, PA, USA 25-26 APRIL 2002, LOS AALMITOS, CA, USA,IEEE COMPUT. SOC, US, (20020425), ISBN 0-7695-1486-3, pages 117 - 124, XP002263346 [A] 1-31 * the whole document *

DOI:   http://dx.doi.org/10.1109/ISVLSI.2002.1016885
 [A]  MILLBERG M ET AL, "The Nostrum backbone - a communication protocol stack for networks on chip", VLSI DESIGN, 2004. PROCEEDINGS. 17TH INTERNATIONAL CONFERENCE ON MUMBAI, INDIA 5-9 JAN. 2004, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, (20040105), ISBN 0-7695-2072-3, pages 693 - 696, XP010679076 [A] 1-31 * the whole document *

DOI:   http://dx.doi.org/10.1109/ICVD.2004.1261005
by applicant   SATHE, S ET AL., "Design of a switching node (router) for On-Chip Networks", AS1C, 2003, PROC. 5TH INTERNATIONAL CONFERENCE, (20031021), vol. 1, pages 75 - 78,
    BARTIC, T, "Highly Scalable Network on Chip for Reconfigurable Systems", PROC. INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-A-CHIP 2003, (20031119), pages 79 - 82,