Extract from the Register of European Patents

About this file: EP1629289

EP1629289 - TESTER ARCHITECTURE FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUITS [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  19.02.2010
Database last updated on 18.03.2019
Most recent event   Tooltip13.04.2010Change: Renewal fee paid 
13.04.2010Deletion: Renewal fee paid 
13.04.2010New entry: Renewal fee paid 
Applicant(s)For all designated states
Teseda Corporation
315 SW 5th Avenue, 1100
Portland, OR 97204-1753 / US
[2006/09]
Inventor(s)01 / LIMAYE, Ajit, M.
10464 NW Forest View Way
Portland, OR 97229 / US
02 / DECHER, Peter, H.
3 Windsor Court
Lake Oswego, OR 97034 / US
03 / NIEHAUS, Horst, Roland
5104 SW View Point Terrace
Portland, OR 97239 / US
 [2006/28]
Former [2006/09]01 / LIMAYE, Ajit, M.
15064 NW Central Drive, Apartment 1303
Portland, OR 97229 / US
02 / DECHER, Peter, H.
3 Windsor Court
Lake Oswego, OR 97034 / US
03 / NIEHAUS, Horst, Roland
5104 SW View Point Terrace
Portland, OR 97239 / US
Representative(s)Hoarton, Lloyd Douglas Charles
Forresters IP LLP
Skygarden
Erika-Mann-Strasse 11
80636 München / DE
[N/P]
Former [2008/44]Hoarton, Lloyd Douglas Charles
Forrester & Boehmert Pettenkoferstrasse 20-22
80336 Munich / DE
Former [2006/09]Hoarton, Lloyd Douglas Charles
Forrester & Boehmert, Pettenkoferstrasse 20-22
80336 München / DE
Application number, filing date04752968.021.05.2004
[2006/09]
WO2004US16068
Priority number, dateUS20030472979P22.05.2003         Original published format: US 472979 P
[2006/09]
Filing languageEN
Procedural languageEN
PublicationType: A1  Application with search report
No.:WO2004106955
Date:09.12.2004
Language:EN
[2004/50]
Type: A1 Application with search report 
No.:EP1629289
Date:01.03.2006
Language:EN
The application has been published by WIPO in one of the EPO official languages on 09.12.2004
[2006/09]
Search report(s)International search report - published on:US09.12.2004
(Supplementary) European search report - dispatched on:EP04.05.2006
ClassificationInternational:G01R31/3185
[2006/24]
Former International [2006/09]G01R31/28
Designated contracting statesAT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HU,   IE,   IT,   LI,   LU,   MC,   NL,   PL,   PT,   RO,   SE,   SI,   SK,   TR [2006/09]
Extension statesALNot yet paid
HRNot yet paid
LTNot yet paid
LVNot yet paid
MKNot yet paid
TitleGerman:TESTERARCHITEKTUR ZUM PRÜFEN INTEGRIERTER HALBLEITERSCHALTUNGEN[2006/09]
English:TESTER ARCHITECTURE FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUITS[2006/09]
French:ARCHITECTURE D'APPAREIL DE TEST DESTINE A TESTER DES CIRCUITS INTEGRES A SEMICONDUCTEUR[2006/09]
Entry into regional phase01.12.2005National basic fee paid 
01.12.2005Search fee paid 
01.12.2005Designation fee(s) paid 
01.12.2005Examination fee paid 
Examination procedure22.12.2004Request for preliminary examination filed
International Preliminary Examining Authority: US
01.12.2005Examination requested  [2006/09]
06.09.2006Despatch of a communication from the examining division (Time limit: M06)
02.02.2007Reply to a communication from the examining division
03.04.2007Despatch of a communication from the examining division (Time limit: M06)
05.10.2007Reply to a communication from the examining division
03.04.2008Despatch of a communication from the examining division (Time limit: M06)
13.10.2008Reply to a communication from the examining division
20.05.2009Communication of intention to grant the patent
01.10.2009Application deemed to be withdrawn, date of legal effect  [2010/12]
04.11.2009Despatch of communication that the application is deemed to be withdrawn, reason: fee for grant / fee for printing not paid in time  [2010/12]
Fees paidRenewal fee
23.03.2006Renewal fee patent year 03
14.05.2007Renewal fee patent year 04
14.05.2008Renewal fee patent year 05
12.05.2009Renewal fee patent year 06
Documents cited:Search[X]US6028439  (ARKIN BRIAN J [US], et al) [X] 1-7 * column A; figures 1-8; claims 1-13 * * column 1, lines 6-34 * * column 2, lines 33-44,56-64 * * column 2, line 65 - column 4, line 8 * * column 6, line 39 - column 7, line 29 * * column 14, line 34 - column 14, line 12 *;
 [X]US2003005375  (KRECH ALAN S [US], et al) [X] 1 * column A; figures 1-3,6; claims 1-9 * * paragraph [0020] *;
 [X]US4931723  (JEFFREY A K [GB], et al) [X] 1 * column A; figures 1-6; claims 1-19 * * column 4, line 3 - column 5, line 28 *;
 [A]US4862067  (BRUNE WILLIAM A [US], et al) [A] 1-7 * column A; figures 1-5; claims 1-36 * * column 2, lines 6-54 *;
 [A]US5497379  (WHETSEL LEE D [US]) [A] 1-7 * column A; figures 1-45; claims 1-23 *
International search[A]US6331770  (SUGAMORI SHIGERU [US]);
 [X]US5396170  (D SOUZA DANIEL [US], et al);
 [Y]US5929650  (PAPPERT BERNARD J [US], et al)