Extract from the Register of European Patents

About this file: EP2261991

EP2261991 - Method of fabricating a high-voltage field-effect transistor [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  29.06.2018
Database last updated on 23.01.2020
FormerThe patent has been granted
Status updated on  21.07.2017
FormerGrant of patent is intended
Status updated on  19.07.2017
FormerExamination is in progress
Status updated on  02.06.2017
FormerGrant of patent is intended
Status updated on  21.02.2017
Most recent event   Tooltip09.11.2018Lapse of the patent in a contracting state
New state(s): GB
published on 12.12.2018  [2018/50]
Applicant(s)For all designated states
Power Integrations, Inc.
5245 Hellyer Avenue
San Jose, California 95138 / US
[2010/50]
Inventor(s)01 / Rumennik, Vladimir
264 Delphi Circle
Los Altos, CA 94022 / US
02 / Disney, Donald R.
10153 Colby Avenue
Cupertino, CA 95014 / US
03 / Ajit, Janardhanan S.
455-E Costa Mesa Terrace
Sunnyvale, 94086 / US
 [2010/50]
Representative(s)Conroy, John , et al
Fish & Richardson P.C.
Highlight Business Towers
Mies-van-der-Rohe-Straße 8
80807 München / DE
[2017/34]
Former [2010/50]Peterreins, Frank
Fish & Richardson P.C. HighLight Business Towers Mies-van-der-Rohe-Strasse 8
80807 München / DE
Application number, filing date10182534.731.01.2000
[2010/50]
Priority number, dateUS1999024502905.02.1999         Original published format: US 245029
[2010/50]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP2261991
Date:15.12.2010
Language:EN
[2010/50]
Type: A3 Search report 
No.:EP2261991
Date:05.01.2011
[2011/01]
Type: B1 Patent specification 
No.:EP2261991
Date:23.08.2017
Language:EN
[2017/34]
Search report(s)(Supplementary) European search report - dispatched on:EP02.12.2010
ClassificationInternational:H01L29/78, H01L29/06, H01L29/08, H01L21/336, H01L21/266, H01L21/74, // H01L29/40, H01L29/10, H01L29/417, H01L29/423
[2010/50]
Designated contracting statesDE,   FR,   GB,   IT,   NL [2017/34]
Former [2010/50]DE,  FR,  GB,  IT,  NL 
TitleGerman:Verfahren zur Herstellung eines Hochspannungsfeldeffekttransistors[2010/50]
English:Method of fabricating a high-voltage field-effect transistor[2010/50]
French:Méthode de fabrication d'un transistor à effet de champ et à haute tension[2010/50]
Examination procedure29.09.2010Examination requested  [2010/50]
10.01.2011Despatch of a communication from the examining division (Time limit: M06)
14.07.2011Reply to a communication from the examining division
28.05.2014Despatch of a communication from the examining division (Time limit: M06)
20.11.2014Reply to a communication from the examining division
10.03.2015Despatch of a communication from the examining division (Time limit: M06)
08.09.2015Reply to a communication from the examining division
13.11.2015Despatch of a communication from the examining division (Time limit: M06)
02.05.2016Reply to a communication from the examining division
22.02.2017Communication of intention to grant the patent
24.05.2017Disapproval of the communication of intention to grant the patent by the applicant or resumption of examination proceedings by the EPO
24.05.2017Fee for grant paid
24.05.2017Fee for publishing/printing paid
18.07.2017Information about intention to grant a patent
18.07.2017Receipt of the translation of the claim(s)
Parent application(s)   TooltipEP00908424.5  / EP1163697
Divisional application(s)The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued (EP20000908424) is  13.05.2008
Opposition(s)24.05.2018No opposition filed within time limit [2018/31]
Fees paidRenewal fee
29.09.2010Renewal fee patent year 03
29.09.2010Renewal fee patent year 04
29.09.2010Renewal fee patent year 05
29.09.2010Renewal fee patent year 06
29.09.2010Renewal fee patent year 07
29.09.2010Renewal fee patent year 08
29.09.2010Renewal fee patent year 09
29.09.2010Renewal fee patent year 10
29.09.2010Renewal fee patent year 11
25.01.2011Renewal fee patent year 12
25.01.2012Renewal fee patent year 13
25.01.2013Renewal fee patent year 14
27.01.2014Renewal fee patent year 15
27.01.2015Renewal fee patent year 16
27.01.2016Renewal fee patent year 17
27.01.2017Renewal fee patent year 18
Lapses during opposition  TooltipIT23.08.2017
NL23.08.2017
FR31.01.2018
GB31.01.2018
[2018/50]
Former [2018/49]IT23.08.2017
NL23.08.2017
FR31.01.2018
Former [2018/28]IT23.08.2017
NL23.08.2017
Former [2018/08]NL23.08.2017
Documents cited:Search[XI]WO9820562  (POWER INTEGRATIONS INC [US]) [X] 12 * page 8, line 9 - page 12, line 19; figure 2 * * page 12, line 32 - page 13, line 29; figure 3 * * page 5, line 11 - page 6, line 23 * [I] 1-11;
 [XA]WO9729518  (SIEMENS AG [DE], et al) [X] 12 * page 12, line 18 - page 3, line 21; figure 6 * [A] 1-11;
 [A]EP0153902  (HAHN MEITNER INST BERLIN GMBH [DE]) [A] 3,4 * page 6, line 16 - page 7, line 7; figures 3-5 *;
 [A]  - TAMBA A ET AL, "CHARACTERISTICS OF BIPOLAR TRANSISTORS WITH VARIOUS DEPTH N+ BURIED LAYERS FORMED BY HIGH ENERGY ION IMPLANTATION", EXTENDED ABSTRACTS OF THE INTERNATIONAL CONFERENCE ON SOLID STATE DEVICES AND MATERIALS, TOKYO, AUG. 24-26, 1988, IEEE, NEW YORK, US, (19880824), vol. 20, no. 1988, pages 141 - 144, XP000042517 [A] 3,4 * figure 1 *
by applicantUS4811075
 US5313082
 US5258636
    - APPELS; VAES, "High Voltage Thin Layer Devices (RESURF Devices)", IEDM TECH. DIGEST, (1979), pages 238 - 241