Extract from the Register of European Patents

About this file: EP2849346

EP2849346 - Mixed-signal circuitry [Right-click to bookmark this link]
StatusThe patent has been granted
Status updated on  19.07.2019
Database last updated on 10.12.2019
FormerGrant of patent is intended
Status updated on  20.03.2019
FormerExamination is in progress
Status updated on  18.11.2016
Most recent event   Tooltip19.07.2019(Expected) grantpublished on 21.08.2019  [2019/34]
Applicant(s)For all designated states
Socionext Inc.
2-10-23 Shin-Yokohama, Kohoku-ku
Yokohama-shi, Kanagawa 222-0033 / JP
Former [2015/12]For all designated states
Fujitsu Semiconductor Limited
2-10-23 Shin-Yokohama Kohoku-ku, Yokohama-shi
Kanagawa 222-0033 / JP
Inventor(s)01 / Dedic, Ian Juso
15 Belvue Road
Northolt, Middlesex UB5 5HW / GB
02 / Danson, John James
43 Denham Way
Stittsville, Ontario K2S 1H5 / CA
Representative(s)Haseltine Lake Kempner LLP
Lincoln House, 5th Floor
300 High Holborn
London WC1V 7JH / GB
Former [2015/12]Lewin, David Nicholas
Haseltine Lake LLP Lincoln House, 5th Floor 300 High Holborn
London WC1V 7JH / GB
Application number, filing date13184044.912.09.2013
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
Type: B1 Patent specification 
Search report(s)(Supplementary) European search report - dispatched on:EP04.04.2014
ClassificationInternational:H03M1/12, // H03M1/46
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2015/32]
Former [2015/12]AL,  AT,  BE,  BG,  CH,  CY,  CZ,  DE,  DK,  EE,  ES,  FI,  FR,  GB,  GR,  HR,  HU,  IE,  IS,  IT,  LI,  LT,  LU,  LV,  MC,  MK,  MT,  NL,  NO,  PL,  PT,  RO,  RS,  SE,  SI,  SK,  SM,  TR 
TitleGerman:Schaltungen für gemischte Signalen[2015/12]
English:Mixed-signal circuitry[2015/12]
French:Circuits à signaux mixtes[2015/12]
Examination procedure25.06.2015Examination requested  [2015/32]
31.03.2016Despatch of a communication from the examining division (Time limit: M04)
26.07.2016Reply to a communication from the examining division
08.11.2016Despatch of a communication from the examining division (Time limit: M04)
23.02.2017Reply to a communication from the examining division
05.10.2018Cancellation of oral proceeding that was planned for 12.10.2018
12.10.2018Date of oral proceedings (cancelled)
21.03.2019Communication of intention to grant the patent
12.07.2019Fee for grant paid
12.07.2019Fee for publishing/printing paid
12.07.2019Receipt of the translation of the claim(s)
Divisional application(s)The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is  31.03.2016
Fees paidRenewal fee
05.08.2015Renewal fee patent year 03
05.07.2016Renewal fee patent year 04
06.07.2017Renewal fee patent year 05
27.09.2018Renewal fee patent year 06
Documents cited:Search[A]  - JING YANG ET AL, "A 1-GS/s 6-bit 6.7-mW ADC in 65-nm CMOS", CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2009. CICC '09. IEEE, IEEE, PISCATAWAY, NJ, USA, (20090913), ISBN 978-1-4244-4071-9, pages 287 - 290, XP031542709 [A] 1-15 * page 287, column r, line 1 - page 288, column l, line 32; figure 1 *
    - JING YANG ET AL, "A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, (20100801), vol. 45, no. 8, doi:10.1109/JSSC.2010.2048139, ISSN 0018-9200, pages 1469 - 1478, XP011314243

DOI:   http://dx.doi.org/10.1109/JSSC.2010.2048139
    - Ehsan Zhian Tabasy ET AL, "C274 978-4-86348-348-4 2013 Symposium on VLSI Circuits Digest of Technical Papers A 6b 10GS/s TI-SAR ADC with Embedded 2-Tap FFE/1-Tap DFE in 65nm CMOS", VLSI Circuits (VLSIC), 2013 Symposium on, Kyoto, (20130614), pages C274 - C275, URL: http://ieeexplore.ieee.org/ielx7/6571720/6578626/06578692.pdf?tp=&arnumber=6578692&isnumber=6578626, (20160317), XP055259091
    - TAO JIANG ET AL, "Single-channel, 1.25-GS/s, 6-bit, loop-unrolled asynchronous SAR-ADC in 40nm-CMOS", CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2010 IEEE, IEEE, PISCATAWAY, NJ, USA, (20100919), ISBN 978-1-4244-5758-8, pages 1 - 4, XP031786654
    - RYOTA SEKIMOTO ET AL, "A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator", ESSCIRC (ESSCIRC), 2011 PROCEEDINGS OF THE, IEEE, (20110912), doi:10.1109/ESSCIRC.2011.6045009, ISBN 978-1-4577-0703-2, pages 471 - 474, XP031976448

DOI:   http://dx.doi.org/10.1109/ESSCIRC.2011.6045009
    - CHANDRAKASAN A P ET AL, "Technologies for Ultradynamic Voltage Scaling", PROCEEDINGS OF THE IEEE, IEEE. NEW YORK, US, (20100201), vol. 98, no. 2, ISSN 0018-9219, pages 191 - 214, XP011300405
    - MAYMANDI-NEJAD ET AL, "DTMOS Technique for Low-Voltage Analog Circuits", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, (20061001), vol. 14, no. 10, doi:10.1109/TVLSI.2006.884174, ISSN 1063-8210, pages 1151 - 1156, XP011142369

DOI:   http://dx.doi.org/10.1109/TVLSI.2006.884174
    - SAMANEH BABAYAN-MASHHADI ET AL, "An offset cancellation technique for comparators using body-voltage trimming", ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, KLUWER ACADEMIC PUBLISHERS, BO, (20120725), vol. 73, no. 3, doi:10.1007/S10470-012-9925-5, ISSN 1573-1979, pages 673 - 682, XP035133364

DOI:   http://dx.doi.org/10.1007/s10470-012-9925-5
    - STEPHEN O'DRISCOLL ET AL, "Adaptive Resolution ADC Array for an Implantable Neural Sensor", IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, IEEE, US, (20110401), vol. 5, no. 2, doi:10.1109/TBCAS.2011.2145418, ISSN 1932-4545, pages 120 - 130, XP011321890

DOI:   http://dx.doi.org/10.1109/TBCAS.2011.2145418
    - Vikram Chaturvedi ET AL, "An 8-to-1 bit 1-MS/s SAR ADC With VGA and Integrated Data Compression for Neural Recording", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS., PISCATAWAY, NJ, USA, (20130201), vol. 21, no. 11, doi:10.1109/TVLSI.2013.2238957, ISSN 1063-8210, pages 2034 - 2044, XP055314228

DOI:   http://dx.doi.org/10.1109/TVLSI.2013.2238957
    - MARCUS YIP ET AL, "A Resolution-Reconfigurable 5-to-10-Bit 0.4-to-1 V Power Scalable SAR ADC for Sensor Applications", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, (20130601), vol. 48, no. 6, doi:10.1109/JSSC.2013.2254551, ISSN 0018-9200, pages 1453 - 1464, XP011510724

DOI:   http://dx.doi.org/10.1109/JSSC.2013.2254551
    - HASSAN SEPEHRIAN ET AL, "A signal-specific successive-approximation analog-to-digital converter", CIRCUITS AND SYSTEMS (ISCAS), 2011 IEEE INTERNATIONAL SYMPOSIUM ON, IEEE, (20110515), doi:10.1109/ISCAS.2011.5937890, ISBN 978-1-4244-9473-6, pages 1624 - 1627, XP031997951

DOI:   http://dx.doi.org/10.1109/ISCAS.2011.5937890
    - MICHAEL TRAKIMAS ET AL, "An Adaptive Resolution Asynchronous ADC Architecture for Data Compression in Energy Constrained Sensing Applications", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, IEEE, US, (20110501), vol. 58, no. 5, doi:10.1109/TCSI.2010.2092132, ISSN 1549-8328, pages 921 - 934, XP011354964

DOI:   http://dx.doi.org/10.1109/TCSI.2010.2092132
    - Ye Xu ET AL, "A low-offset dynamic comparator using bulk biasing technique in digital 65nm CMOS technology", Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on, Piscataway, NJ, USA, (20101101), doi:10.1109/ICSICT.2010.5667838, ISBN 978-1-4244-5797-7, pages 102 - 104, XP055471519

DOI:   http://dx.doi.org/10.1109/ICSICT.2010.5667838
    - Junjie Lu ET AL, "A low-power dynamic comparator with time-domain bulk-driven offset cancellation", 2012 IEEE International Symposium on Circuits and Systems, (20120501), doi:10.1109/ISCAS.2012.6271807, ISBN 978-1-4673-0217-3, pages 2493 - 2496, XP055471520

DOI:   http://dx.doi.org/10.1109/ISCAS.2012.6271807
    - JON GUERBER ET AL, "A 10b Ternary SAR ADC with decision time quantization based redundancy", SOLID STATE CIRCUITS CONFERENCE (A-SSCC), 2011 IEEE ASIAN, IEEE, (20111114), doi:10.1109/ASSCC.2011.6123605, ISBN 978-1-4577-1784-0, pages 65 - 68, XP032090580

DOI:   http://dx.doi.org/10.1109/ASSCC.2011.6123605
    - TAO JIANG ET AL, "A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, (20121001), vol. 47, no. 10, doi:10.1109/JSSC.2012.2204543, ISSN 0018-9200, pages 2444 - 2453, XP011466450

DOI:   http://dx.doi.org/10.1109/JSSC.2012.2204543
by applicantEP2211468