Extract from the Register of European Patents

About this file: EP2814254

EP2814254 - Combined parallel and pipelined video encoder [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  20.07.2018
Database last updated on 16.10.2019
FormerExamination is in progress
Status updated on  18.04.2017
Most recent event   Tooltip20.07.2018Application deemed to be withdrawnpublished on 22.08.2018  [2018/34]
Applicant(s)For all designated states
OCT Circuit Technologies International Limited
Unit 32, the Hyde Building The Park, Carrickmines
Dublin 18 / IE
[2017/03]
Former [2014/51]For all designated states
ST-Ericsson SA
Chemin du Champ-des-Filles 39
1228 Plan-les-Ouates / CH
Inventor(s)01 / Pierson, Valerie
9 rue Antoine Polotti
38400 Saint Martin d'Heres / FR
02 / Migeotte, Vincent
28 rue de Clapieres
38120 Saint-Egreve / FR
 [2014/51]
Representative(s)Grünecker Patent- und Rechtsanwälte PartG mbB
Leopoldstraße 4
80802 München / DE
[N/P]
Former [2014/51]Cabinet Plasseraud
52, rue de la Victoire
75440 Paris Cedex 09 / FR
Application number, filing date13305197.921.02.2013
[2014/51]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP2814254
Date:17.12.2014
Language:EN
[2014/51]
Search report(s)(Supplementary) European search report - dispatched on:EP08.05.2013
ClassificationInternational:H04N19/00
[2014/51]
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2015/29]
Former [2014/51]AL,  AT,  BE,  BG,  CH,  CY,  CZ,  DE,  DK,  EE,  ES,  FI,  FR,  GB,  GR,  HR,  HU,  IE,  IS,  IT,  LI,  LT,  LU,  LV,  MC,  MK,  MT,  NL,  NO,  PL,  PT,  RO,  RS,  SE,  SI,  SK,  SM,  TR 
Extension statesBANot yet paid
MENot yet paid
TitleGerman:Kombinierter paralleler und zeitverschachtelter Videocodierer[2014/51]
English:Combined parallel and pipelined video encoder[2014/51]
French:Codeur vidéo en pipeline et parallèle combinée[2014/51]
Examination procedure03.06.2015Amendment by applicant (claims and/or description)
03.06.2015Examination requested  [2015/29]
26.10.2015Despatch of a communication from the examining division (Time limit: M04)
11.02.2016Reply to a communication from the examining division
06.04.2017Despatch of a communication from the examining division (Time limit: M04)
22.06.2017Reply to a communication from the examining division
08.11.2017Despatch of a communication from the examining division (Time limit: M04)
20.03.2018Application deemed to be withdrawn, date of legal effect  [2018/34]
16.04.2018Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time  [2018/34]
Divisional application(s)The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is  26.10.2015
Fees paidRenewal fee
24.02.2015Renewal fee patent year 03
25.02.2016Renewal fee patent year 04
23.02.2017Renewal fee patent year 05
Penalty fee
Additional fee for renewal fee
28.02.201806   M06   Not yet paid
Documents cited:Search[X]WO2007129433  (MINAMI TOSHIHIRO [JP]) [X] 1,4,6-9,11,13,14 * abstract *;
 [Y]EP2528331  (RENESAS ELECTRONICS CORP [JP]) [Y] 1-14 * figures 2, 3, 4 *;
 [Y]  - TUNG-CHIEN CHEN ET AL, "Hardware architecture design of an H.264/AVC video codec", DESIGN AUTOMATION, 2006. ASIA AND SOUTH PACIFIC CONFERENCE ON JAN. 24, 2006, PISCATAWAY, NJ, USA,IEEE, (20060124), doi:10.1109/ASPDAC.2006.1594776, ISBN 978-0-7803-9451-3, pages 750 - 757, XP010901163 [Y] 1-14 * pages 752-753; figure 3 *

DOI:   http://dx.doi.org/10.1109/ASPDAC.2006.1594776
by applicantUS2009274213