Extract from the Register of European Patents

About this file: EP2959390

EP2959390 - INTER-SET WEAR-LEVELING FOR CACHES WITH LIMITED WRITE ENDURANCE [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  27.04.2018
Database last updated on 19.11.2019
FormerGrant of patent is intended
Status updated on  17.07.2017
Most recent event   Tooltip27.04.2018Application deemed to be withdrawnpublished on 30.05.2018  [2018/22]
Applicant(s)For all designated states
Qualcomm Incorporated
5775 Morehouse Drive
San Diego, CA 92121 / US
[2016/01]
Inventor(s)01 / DONG, Xiangyu
5775 Morehouse Drive
San Diego California 92121 / US
 [2016/01]
Representative(s)Dunlop, Hugh Christopher , et al
Maucher Jenkins
26 Caxton Street
London SW1H 0RJ / GB
[N/P]
Former [2016/01]Dunlop, Hugh Christopher , et al
RGC Jenkins & Co.
26 Caxton Street
London SW1H 0RJ / GB
Application number, filing date14709777.812.02.2014
[2016/01]
WO2014US15994
Priority number, dateUS20131377240021.02.2013         Original published format: US201313772400
[2016/01]
Filing languageEN
Procedural languageEN
PublicationType: A1  Application with search report
No.:WO2014130317
Date:28.08.2014
Language:EN
[2014/35]
Type: A1 Application with search report 
No.:EP2959390
Date:30.12.2015
Language:EN
The application has been published by WIPO in one of the EPO official languages on 28.08.2014
[2015/53]
Search report(s)International search report - published on:EP28.08.2014
ClassificationInternational:G06F12/02, G06F12/0802, G06F12/0864, G06F12/0891
[2017/28]
Former International [2016/01]G06F12/02, G06F12/08
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2016/01]
TitleGerman:ABNUTZUNGSAUSGLEICH ZWISCHEN SÄTZEN FÜR CACHESPEICHER MIT BEGRENZTER SCHREIBDAUERHAFTIGKEIT[2016/01]
English:INTER-SET WEAR-LEVELING FOR CACHES WITH LIMITED WRITE ENDURANCE[2016/01]
French:NIVELLEMENT D'USURE ENTRE ENSEMBLES POUR DES ANTÉMÉMOIRES À ENDURANCE D'ÉCRITURE LIMITÉE[2016/01]
Entry into regional phase27.07.2015National basic fee paid 
27.07.2015Designation fee(s) paid 
27.07.2015Examination fee paid 
Examination procedure19.12.2014Request for preliminary examination filed
International Preliminary Examining Authority: EP
27.07.2015Examination requested  [2015/53]
14.04.2016Amendment by applicant (claims and/or description)
18.07.2017Communication of intention to grant the patent
29.11.2017Application deemed to be withdrawn, date of legal effect  [2018/22]
15.01.2018Despatch of communication that the application is deemed to be withdrawn, reason: fee for grant / fee for printing not paid in time  [2018/22]
Divisional application(s)The date of the Examining Division's first communication in respect of the earliest application for which a communication has been issued is  18.07.2017
Fees paidRenewal fee
14.12.2015Renewal fee patent year 03
07.02.2017Renewal fee patent year 04
Penalty fee
Additional fee for renewal fee
28.02.201805   M06   Not yet paid
Cited inInternational search[XYI]  - MOINUDDIN K. QURESHI ET AL, "Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling", PROCEEDINGS OF THE 42ND ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, MICRO-42, New York, New York, USA, (20090101), doi:10.1145/1669112.1669117, ISBN 978-1-60-558798-1, page 14, XP055120713 [X] 1-4,9-15,17,19 * Chapter 4 Start-Gap wear leveling * * Chapter 5 Address space randomization * [Y] 5-7 [I] 8,16,18,20

DOI:   http://dx.doi.org/10.1145/1669112.1669117
 [Y]  - AMIN JADIDI ET AL, "High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement", LOW POWER ELECTRONICS AND DESIGN (ISLPED) 2011 INTERNATIONAL SYMPOSIUM ON, IEEE, (20110801), doi:10.1109/ISLPED.2011.5993611, ISBN 978-1-61284-658-3, pages 79 - 84, XP032038792 [Y] 5-7 * Chapter III. WRITE MANAGEMENT POLICIES *

DOI:   http://dx.doi.org/10.1109/ISLPED.2011.5993611
 [A]  - PING ZHOU ET AL, "A durable and energy efficient main memory using phase change memory technology", ACM SIGARCH COMPUTER ARCHITECTURE NEWS, (20090615), vol. 37, no. 3, doi:10.1145/1555815.1555759, ISSN 0163-5964, page 14, XP055120565 [A] 1-20 * Chapter 3 Improving the endurance of PCM *

DOI:   http://dx.doi.org/10.1145/1555815.1555759
 [XP]  - JUE WANG ET AL, "i 2 WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variations", HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA2013), 2013 IEEE 19TH INTERNATIONAL SYMPOSIUM ON, IEEE, (20130223), doi:10.1109/HPCA.2013.6522322, ISBN 978-1-4673-5585-8, pages 234 - 245, XP032415823 [XP] 1-20 * Chapter 5 Starting from inter-set write variations * * Chapter 6 Intra-set variation: a more severe issue *

DOI:   http://dx.doi.org/10.1109/HPCA.2013.6522322