Extract from the Register of European Patents

About this file: EP3082168

EP3082168 - INSULATED GATE BIPOLAR TRANSISTOR AND PRODUCTION METHOD THEREFOR [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  08.06.2018
Database last updated on 24.08.2019
FormerRequest for examination was made
Status updated on  22.02.2018
Most recent event   Tooltip08.06.2018Application deemed to be withdrawnpublished on 11.07.2018  [2018/28]
Applicant(s)For all designated states
ULVAC, Inc.
2500 Hagisono
Chigasaki-shi, Kanagawa 253-8543 / JP
[2016/42]
Inventor(s)01 / TONARI, Kazuhiko
c/o ULVAC INC.
2500 Hagisono
Chigasaki-shi Kanagawa 253-8543 / JP
02 / NAKAGAWA, Akio
c/o ULVAC INC.
2500 Hagisono
Chigasaki-shi Kanagawa 253-8543 / JP
03 / YOKOO, Hidekazu
c/o ULVAC INC.
2500 Hagisono
Chigasaki-shi Kanagawa 253-8543 / JP
04 / SUZUKI, Hideo
c/o ULVAC INC.
2500 Hagisono
Chigasaki-shi Kanagawa 253-8543 / JP
 [2016/42]
Representative(s)Markfort, Iris-Anne Lucie
Lorenz & Kollegen
Patentanwälte Partnerschaftsgesellschaft mbB
Alte Ulmer Straße 2
89522 Heidenheim / DE
[2016/42]
Application number, filing date14869846.702.12.2014
[2016/42]
WO2014JP06010
Priority number, dateJP2013025485010.12.2013         Original published format: JP 2013254850
[2016/42]
Filing languageJA
Procedural languageEN
PublicationType: A1  Application with search report
No.:WO2015087507
Date:18.06.2015
Language:JA
[2015/24]
Type: A1 Application with search report 
No.:EP3082168
Date:19.10.2016
Language:EN
[2016/42]
Search report(s)International search report - published on:JP18.06.2015
(Supplementary) European search report - dispatched on:EP20.06.2017
ClassificationInternational:H01L29/739, H01L21/265, H01L21/336, H01L29/12, H01L29/78
[2016/42]
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2016/42]
TitleGerman:BIPOLARER TRANSISTOR MIT ISOLIERTEM GATE UND HERSTELLUNGSVERFAHREN DAFÜR[2016/42]
English:INSULATED GATE BIPOLAR TRANSISTOR AND PRODUCTION METHOD THEREFOR[2016/42]
French:TRANSISTOR BIPOLAIRE À GRILLE ISOLÉE ET SON PROCÉDÉ DE FABRICATION[2016/42]
Entry into regional phase08.06.2016Translation filed 
08.06.2016National basic fee paid 
08.06.2016Search fee paid 
08.06.2016Designation fee(s) paid 
08.06.2016Examination fee paid 
Examination procedure08.06.2016Examination requested  [2016/42]
18.01.2018Application deemed to be withdrawn, date of legal effect  [2018/28]
23.02.2018Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time  [2018/28]
Fees paidRenewal fee
22.12.2016Renewal fee patent year 03
Penalty fee
Additional fee for renewal fee
31.12.201704   M06   Not yet paid
Documents cited:Search[XYI]JP2010272741  (FUJI ELECTRIC SYSTEMS CO LTD) [X] 1,6,8 * paragraph [0012] - paragraph [0018] * * abstract * [Y] 2-5 [I] 7;
 [XY]US2012248576  (SCHMIDT GERHARD [AT], et al) [X] 8 * paragraph [0009] * * paragraph [0053] - paragraph [0055] * * figure 14 * [Y] 1-7;
 [XY]US2012326277  (LEE SEUNG-CHUL [KR], et al) [X] 8 * paragraph [0060] - paragraph [0071] * * figures 5 - 6B(b) * [Y] 1-7;
 [XY]JP2004146679  (TOYOTA CENTRAL RES & DEV, et al) [X] 8 * paragraph [0035] - paragraph [0039] * * figures 3(a)-3(e) * [Y] 1-7
International search[Y]WO2013147275  (FUJI ELECTRIC CO LTD [JP]);
 [Y]WO2009025337  (SUMCO CORP [JP], et al);
 [Y]JP2004146679  (TOYOTA CENTRAL RES & DEV, et al);
 [Y]WO2013141181  (FUJI ELECTRIC CO LTD [JP])
by applicantJP20030533047