Extract from the Register of European Patents

About this file: EP3163616

EP3163616 - SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE [Right-click to bookmark this link]
StatusThe patent has been granted
Status updated on  01.11.2019
Database last updated on 21.02.2020
FormerGrant of patent is intended
Status updated on  20.06.2019
FormerRequest for examination was made
Status updated on  03.11.2017
FormerThe application has been published
Status updated on  31.03.2017
Most recent event   Tooltip01.11.2019(Expected) grantpublished on 04.12.2019  [2019/49]
Applicant(s)For all designated states
MediaTek Inc.
No. 1, Dusing Road 1st
Science-Based Industrial Park
Hsin-Chu 300 / TW
[2017/18]
Inventor(s)01 / LIAO, Chun-Neng
2F., No.6, Minzu St., Yonghe Dist.
New Taipei City 234 / TW
02 / CHIANG, Meng-Hsin
11F., No.11, Shelun St., Hsinchu County
Zhubei City 302 / TW
03 / CHANG, Chun-Wei
9F., No.124, Ln. 162, Jingye 3rd Rd., Zhongshan
Dist.
Taipei City 104 / TW
04 / UNG, Chee-Kong
No.18, Aly. 5, Ln. 1200, Minghu Rd., East Dist.
Hsinchu City 300 / TW
05 / LI, Ching-Chih
12F., No.267, Siyuan Rd., Sindian Dist.
New Taipei City 231 / TW
 [2017/18]
Representative(s)Goddar, Heinz J.
Boehmert & Boehmert
Anwaltspartnerschaft mbB
Pettenkoferstrasse 22
80336 München / DE
[2019/49]
Former [2017/18]Goddar, Heinz J.
Boehmert & Boehmert
Anwaltspartnerschaft mbB
Patentanwälte Rechtsanwälte
Pettenkoferstrasse 20-22
80336 München / DE
Application number, filing date16192005.303.10.2016
[2017/18]
Priority number, dateUS201562241240P14.10.2015         Original published format: US 201562241240 P
US20161527447323.09.2016         Original published format: US201615274473
[2017/18]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP3163616
Date:03.05.2017
Language:EN
[2017/18]
Type: B1 Patent specification 
No.:EP3163616
Date:04.12.2019
Language:EN
[2019/49]
Search report(s)(Supplementary) European search report - dispatched on:EP04.04.2017
ClassificationInternational:H01L25/16, H01L23/64, H03H7/06, H03K5/1252
[2019/26]
Former International [2017/18]H01L25/16, H01L23/64, H03H7/06
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2017/49]
Former [2017/18]AL,  AT,  BE,  BG,  CH,  CY,  CZ,  DE,  DK,  EE,  ES,  FI,  FR,  GB,  GR,  HR,  HU,  IE,  IS,  IT,  LI,  LT,  LU,  LV,  MC,  MK,  MT,  NL,  NO,  PL,  PT,  RO,  RS,  SE,  SI,  SK,  SM,  TR 
TitleGerman:VORRICHTUNG MIT EINER INTEGRIERTEN HALBLEITERSCHALTUNG[2017/18]
English:SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE[2017/18]
French:CIRCUIT INTÉGRÉ À SEMI-CONDUCTEUR[2017/18]
Examination procedure03.10.2016Date on which the examining division has become responsible
26.10.2017Amendment by applicant (claims and/or description)
26.10.2017Examination requested  [2017/49]
21.06.2019Communication of intention to grant the patent
21.10.2019Fee for grant paid
21.10.2019Fee for publishing/printing paid
21.10.2019Receipt of the translation of the claim(s)
Fees paidRenewal fee
11.10.2018Renewal fee patent year 03
29.10.2019Renewal fee patent year 04
Documents cited:Search[IAY]US2012081193  (SHIRAKAWA KAZUHIRO [JP], et al) [I] 1,3-5 * paragraph [0056] * [A] 9-13 [Y] 2,6-8;
 [IAY]US2007279882  (WEIR STEVE [US], et al) [I] 1,3-5 * paragraph [0143] * [A] 9-13 [Y] 2,6-8;
 [IAY]US2006139123  (TANG GEORGE [US]) [I] 1,3-5 * claim 8 * [A] 9-13 [Y] 2,6-8;
 [Y]US2015207485  (HSU YEN WEI [TW], et al) [Y] 2 * paragraph [0002] *;
 [Y]US2011180898  (TOMISHIMA ATSUSHI [JP], et al) [Y] 6-8 * figures 7,8 *;
 [Y]JPS6175558  (NEC CORP) [Y] 6-8 * figures 1,2 *