Extract from the Register of European Patents

About this file: EP3304586

EP3304586 - A METHOD OF MANUFACTURING SILICON GERMANIUM-ON-INSULATOR [Right-click to bookmark this link]
StatusExamination is in progress
Status updated on  04.01.2019
Database last updated on 18.01.2020
FormerRequest for examination was made
Status updated on  09.03.2018
FormerThe international publication has been made
Status updated on  09.12.2016
Most recent event   Tooltip13.11.2019New entry: Reply to examination report 
Applicant(s)For all designated states
GlobalWafers Co., Ltd.
No. 8 Industrial East Road 2
Science-Based Industrial Park
Hsinchu, Taiwan R.O.C. / TW
[2019/11]
Former [2018/15]For all designated states
SunEdison Semiconductor Limited
15-01 Straits Trading Building
9 Battery Road
Singapore 049910 / SG
Inventor(s)01 / THOMAS, Shawn G.
501 Pearl Drive
St. Peters, Missouri 63376 / US
02 / WANG, Gang
501 Pearl Drive
St. Peters, Missouri 63376 / US
 [2018/15]
Representative(s)Parchmann, Stefanie
Maiwald Patentanwalts- und
Rechtsanwaltsgesellschaft mbH
Elisenhof
Elisenstraße 3
80335 München / DE
[N/P]
Former [2018/15]Parchmann, Stefanie
Maiwald Patentanwalts GmbH
Elisenhof
Elisenstraße 3
80335 München / DE
Application number, filing date16726253.418.05.2016
[2018/15]
WO2016US33097
Priority number, dateUS201562169178P01.06.2015         Original published format: US 201562169178 P
[2018/15]
Filing languageEN
Procedural languageEN
PublicationType: A1  Application with search report
No.:WO2016196011
Date:08.12.2016
Language:EN
[2016/49]
Type: A1 Application with search report 
No.:EP3304586
Date:11.04.2018
Language:EN
The application has been published by WIPO in one of the EPO official languages on 08.12.2016
[2018/15]
Search report(s)International search report - published on:EP08.12.2016
ClassificationInternational:H01L21/762, H01L21/02
[2018/15]
Designated contracting statesAL,   AT,   BE,   BG,   CH,   CY,   CZ,   DE,   DK,   EE,   ES,   FI,   FR,   GB,   GR,   HR,   HU,   IE,   IS,   IT,   LI,   LT,   LU,   LV,   MC,   MK,   MT,   NL,   NO,   PL,   PT,   RO,   RS,   SE,   SI,   SK,   SM,   TR [2018/15]
TitleGerman:VERFAHREN ZUR HERSTELLUNG VON SILICIUM-GERMANIUM AUF ISOLATOR[2018/15]
English:A METHOD OF MANUFACTURING SILICON GERMANIUM-ON-INSULATOR[2018/15]
French:PROCÉDÉ DE FABRICATION DE SILICIUM-GERMANIUM SUR ISOLANT[2018/15]
Entry into regional phase19.12.2017National basic fee paid 
19.12.2017Designation fee(s) paid 
19.12.2017Examination fee paid 
Examination procedure19.12.2017Examination requested  [2018/15]
19.12.2017Date on which the examining division has become responsible
30.05.2018Amendment by applicant (claims and/or description)
07.01.2019Despatch of a communication from the examining division (Time limit: M04)
30.04.2019Reply to a communication from the examining division
30.07.2019Despatch of a communication from the examining division (Time limit: M04)
13.11.2019Reply to a communication from the examining division
Fees paidRenewal fee
29.05.2018Renewal fee patent year 03
28.05.2019Renewal fee patent year 04
Cited inInternational search[A]US2005054175  (BAUER MATTHIAS [US]) [A] 8,10-12,17,19 * paragraphs [0035] , [0041] , [0042]; figure 8 *;
 [A]US2003013305  (SUGII NOBUYUKI [JP], et al) [A] 1,22 * paragraph [0034] - paragraph [0094] *
 [I]  - BRUNNER K ET AL, "Molecular beam epitaxy growth and thermal stability of Si"1"-"xGe"x layers on extremely thin silicon-on-insulator substrates", THIN SOLID FILMS, ELSEVIER-SEQUOIA S.A. LAUSANNE, CH, (19980526), vol. 321, no. 1-2, doi:10.1016/S0040-6090(98)00481-7, ISSN 0040-6090, pages 245 - 250, XP004147928 [I] 1-35 * page 246 - page 248; figure 1d *

DOI:   http://dx.doi.org/10.1016/S0040-6090(98)00481-7
by applicantUS5189500
    - M. L. LEE, "Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors", J. APPL. PHYS., (2005), vol. 97, page 011101
    - Z. CHENG, "Electron Mobility Enhancement in Strained-Si n-MOSFETs Fabricated on SiGe-on-Insulator (SGOI) Substrates", IEEE ELECT. DEV. LETT., (2001), vol. 22, no. 7, page 321
    - W.C. O'MARA ET AL., Handbook of Semiconductor Silicon Technology, NOYES PUBLICATIONS