EP4167097 - HANDLING MEMORY-LINES IN A MULTI-CORE PROCESSOR [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 01.03.2024 Database last updated on 11.11.2024 | |
Former | The application has been published Status updated on 17.03.2023 | Most recent event Tooltip | 01.03.2024 | Application deemed to be withdrawn | published on 03.04.2024 [2024/14] | Applicant(s) | For all designated states Universidad de Murcia Edif. Eisum (Facultad Medicina). 3ª planta. Campus Espinardo 30071 Murcia / ES | [2023/16] | Inventor(s) | 01 /
GÓMEZ HERNÁNDEZ, Eduardo José 30100 Murcia / ES | 02 /
CEBRIÁN GONZÁLEZ, Juan Manuel 30100 Murcia / ES | 03 /
TITOS GIL, José Rubén 30100 Murcia / ES | 04 /
ROS BARDISA, Alberto 30100 Murcia / ES | 05 /
KAXIRAS, Stefanos 30100 Murcia / ES | [2023/16] | Representative(s) | ZBM Patents - Zea, Barlocci & Markvardsen Rambla de Catalunya, 123 08008 Barcelona / ES | [N/P] |
Former [2023/16] | ZBM Patents - Zea, Barlocci & Markvardsen Rambla Catalunya, 123 08008 Barcelona / ES | Application number, filing date | 21382919.5 | 13.10.2021 | [2023/16] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP4167097 | Date: | 19.04.2023 | Language: | EN | [2023/16] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 29.04.2022 | Classification | IPC: | G06F12/0864, G06F12/14 | [2023/16] | CPC: |
G06F12/0864 (EP);
G06F12/1466 (EP)
| Designated contracting states | AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LI, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR [2023/16] | Extension states | BA | Not yet paid | ME | Not yet paid | Validation states | KH | Not yet paid | MA | Not yet paid | MD | Not yet paid | TN | Not yet paid | Title | German: | HANDHABUNG VON SPEICHERZEILEN IN EINEM MEHRKERNPROZESSOR | [2023/16] | English: | HANDLING MEMORY-LINES IN A MULTI-CORE PROCESSOR | [2023/16] | French: | TRAITEMENT DE LIGNES DE MÉMOIRE DANS UN PROCESSEUR MULTIC UR | [2023/16] | Examination procedure | 20.10.2023 | Application deemed to be withdrawn, date of legal effect [2024/14] | 27.11.2023 | Despatch of communication that the application is deemed to be withdrawn, reason: examination fee not paid in time [2024/14] | Fees paid | Penalty fee | Additional fee for renewal fee | 31.10.2023 | 03   M06   Not yet paid |
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [Y]WO2009125249 (FREESCALE SEMICONDUCTOR INC [US], et al) [Y] 6,7 * paragraph [0024] - paragraph [0028] ** figures 1-5; claims 1-20 *; | [Y]US2014189238 (ZEI LI-GAO [DE], et al) [Y] 2 * paragraph [0027] - paragraph [0030] * * figures 1-5; claims 1-21 *; | [Y]US2016179681 (GREENSPAN DANIEL [IL], et al) [Y] 3,4 * paragraph [0029] - paragraph [0033] * * figures 1-12; claims 1-20 *; | [Y]US2018165214 (FARMAHINI FARAHANI AMIN [US], et al) [Y] 10 * paragraph [0012] - paragraph [0023] * * figures 1-8; claims 1-20 *; | [XY]US2019324905 (ROS ALBERTO [ES], et al) [X] 1,5,8,9,11-15 * paragraph [0010] - paragraph [0081] * * figures 1-15; claims 1-21 * [Y] 2-4,6,7,10 |