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EP0126292
European procedure
Extract from the Register of European Patents
EP About this file: EP0126292
| EP0126292 - Semiconductor device having an element isolation layer and method of manufacturing the same [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 29.09.1988 Database last updated on 26.03.2025 | Most recent event Tooltip | 29.09.1988 | No opposition filed within time limit | published on 17.11.1988 [1988/46] | Applicant(s) | For all designated states Kabushiki Kaisha Toshiba 72, Horikawa-cho, Saiwai-ku Kawasaki-shi Kanagawa-ken 210-8572 / JP | [N/P] |
| Former [1984/48] | For all designated states KABUSHIKI KAISHA TOSHIBA 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210, Tokyo / JP | Inventor(s) | 01 /
Maeda, Satoshi c/o Patent Division Kabushiki Kaisha Toshiba 1-1 Shibaura 1-chome Minato-ku Tokyo 105 / JP | 02 /
Iwai, Hiroshi c/o Patent Division Kabushiki Kaisha Toshiba 1-1 Shibaura 1-chome Minato-ku Tokyo 105 / JP | [1984/48] | Representative(s) | Lehn, Werner, et al Hoffmann Eitle, Patent- und Rechtsanwälte, Postfach 81 04 20 81904 München / DE | [N/P] |
| Former [1984/48] | Lehn, Werner, Dipl.-Ing., et al Hoffmann, Eitle & Partner, Patentanwälte, Postfach 81 04 20 D-81904 München / DE | Application number, filing date | 84104279.9 | 16.04.1984 | [1984/48] | Priority number, date | JP19830070426 | 21.04.1983 Original published format: JP 7042683 | JP19830070427 | 21.04.1983 Original published format: JP 7042783 | JP19830070428 | 21.04.1983 Original published format: JP 7042883 | JP19830076453 | 30.04.1983 Original published format: JP 7645383 | [1984/48] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0126292 | Date: | 28.11.1984 | Language: | EN | [1984/48] | Type: | B1 Patent specification | No.: | EP0126292 | Date: | 02.12.1987 | Language: | EN | [1987/49] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 13.08.1984 | Classification | IPC: | H01L21/20, H01L21/76 | [1984/48] | CPC: |
H01L21/76294 (EP,US);
H01L21/02381 (EP,US);
H01L21/0242 (EP,US);
H01L21/02532 (EP,US);
H01L21/02639 (EP,US);
H01L21/268 (EP,US)
| Designated contracting states | DE, FR, GB, IT [1984/48] | Title | German: | Halbleitervorrichtung mit einer Schicht zur Isolation der Elemente und Verfahren zu ihrer Herstellung | [1984/48] | English: | Semiconductor device having an element isolation layer and method of manufacturing the same | [1984/48] | French: | Dispositif semi-conducteur avec une couche d'isolement entre les éléments et procédé de fabrication | [1984/48] | Examination procedure | 16.04.1984 | Examination requested [1984/48] | 13.11.1985 | Despatch of a communication from the examining division (Time limit: M06) | 13.05.1986 | Reply to a communication from the examining division | 18.02.1987 | Despatch of communication of intention to grant (Approval: ) | 26.05.1987 | Communication of intention to grant the patent | 12.08.1987 | Fee for grant paid | 12.08.1987 | Fee for publishing/printing paid | Opposition(s) | 03.09.1988 | No opposition filed within time limit [1988/46] | Fees paid | Renewal fee | 18.04.1986 | Renewal fee patent year 03 | 15.04.1987 | Renewal fee patent year 04 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]US4101350 (POSSLEY GLEN G, et al); | [A]DE3225398 (NIPPON ELECTRIC CO [JP]); | [A]US3966501 (NOMURA KOUSI, et al); | [A]US3728161 (MOLINE R) | [X] - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 25, no. 7A, December 1982, New York, USA; V.J. SILVESTRI et al. "Practical selective epitaxial process for oxide isolation", pages 3329-3330 | [A] - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 24, no. 9, February 1982, New York, USA; W.K. CHU et al. "Process for producing dielectrically isolated single crystal silicon", pages 4734-4735 | [A] - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 21, no. 5, October 1978, New York, USA; H.B. POGGE "Reestablishing parallelism after RIE etching", pages 1849-1850 |