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Extract from the Register of European Patents

EP About this file: EP0125174

EP0125174 - A method of fabricating integrated circuit structures using replica patterning [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  02.02.1990
Database last updated on 17.07.2024
Most recent event   Tooltip07.07.2007Change - inventorpublished on 08.08.2007  [2007/32]
Applicant(s)For all designated states
FAIRCHILD SEMICONDUCTOR CORPORATION
10400 Ridgeview Court P.O. Box 1500
Cupertino, California 95014 / US
[N/P]
Former [1988/35]For all designated states
FAIRCHILD SEMICONDUCTOR CORPORATION
10400 Ridgeview Court P.O. Box 1500
Cupertino, California 95014 / US
Former [1984/46]For all designated states
FAIRCHILD CAMERA & INSTRUMENT CORPORATION
464 Ellis Street
Mountain View California 94042 / US
Inventor(s)01 / Berry, Robert L.
20192 North Cove Square
Cupertino California 95014 / US
[1984/46]
Representative(s)Sparing Röhl Henseler
Postfach 14 04 43
40074 Düsseldorf / DE
[N/P]
Former [1988/35]Sparing Röhl Henseler Patentanwälte
Postfach 14 04 43
D-40074 Düsseldorf / DE
Former [1985/04]Chareyron, Lucien
Service Brevets Patent Department Etudes et Productions Schlumberger BP 202
F-92142 Clamart Cédex / FR
Former [1984/46]Chareyron, Lucien
Schlumberger Limited Service Brevets c/o Giers, B.P. 121 12, place des Etats-Unis
F-92124 Montrouge Cedex / FR
Application number, filing date84400874.802.05.1984
[1984/46]
Priority number, dateUS1983049062202.05.1983         Original published format: US 490622
[1984/46]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0125174
Date:14.11.1984
Language:EN
[1984/46]
Type: A3 Search report 
No.:EP0125174
Date:14.01.1987
Language:EN
[1987/03]
Search report(s)(Supplementary) European search report - dispatched on:EP24.11.1986
ClassificationIPC:H01L21/00
[1984/46]
CPC:
H01L21/033 (EP,US); H01L29/7325 (EP,US); Y10S438/947 (EP,US)
Designated contracting statesDE,   FR,   GB,   IT,   NL [1984/46]
TitleGerman:Verfahren zum Herstellen von integrierten Schaltungsstrukturen mit "Replica Patterning"[1984/46]
English:A method of fabricating integrated circuit structures using replica patterning[1984/46]
French:Procédé de fabrication de structures de circuits intégrés par "replica patterning"[1984/46]
File destroyed:02.03.1998
Examination procedure25.06.1987Examination requested  [1987/35]
14.03.1989Despatch of a communication from the examining division (Time limit: M06)
26.09.1989Application deemed to be withdrawn, date of legal effect  [1990/12]
25.10.1989Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time  [1990/12]
Fees paidRenewal fee
19.03.1986Renewal fee patent year 03
01.04.1987Renewal fee patent year 04
23.03.1988Renewal fee patent year 05
29.03.1989Renewal fee patent year 06
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Documents cited:Search[A]FR2130397  (PHILIPS NV);
 [AD]US3940288  (TAKAGI MIKIO, et al);
 [Y]WO8000639  (WESTERN ELECTRIC CO [US]);
 [Y]EP0032999  (IBM [US])
 [A]  - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 21, no. 12, May 1979, pages 4852-4854, New York, US; I. ANTIPOV: "Mask-independent short channel MOS"
 [A]  - IBM TECHNICAL DISCLOSURE BULLETIN, vol. 17, no. 10, March 1975, pages 2942,2943, New York, US; B.C. FENG et al.: "Ion-implanted emitters"
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.