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EP0253530
European procedure
Extract from the Register of European Patents
EP About this file: EP0253530
| EP0253530 - Dynamically reconfigurable array logic [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 13.08.1992 Database last updated on 10.12.2024 | Most recent event Tooltip | 13.08.1992 | No opposition filed within time limit | published on 30.09.1992 [1992/40] | Applicant(s) | For all designated states HONEYWELL INC. Honeywell Plaza Minneapolis, MN 55408 / US | [N/P] |
| Former [1988/03] | For all designated states HONEYWELL INC. Honeywell Plaza Minneapolis Minnesota 55408 / US | Inventor(s) | 01 /
Henry, Mathew W. 206 Columbia Drive, S.E. Apt. B Alberquerque New Mexico 87106 / US | [1988/03] | Representative(s) | Singleton, Jeffrey, et al Eric Potter Clarkson, Park View House, 58 The Ropewalk Nottingham NG1 5DD / GB | [N/P] |
| Former [1988/03] | Singleton, Jeffrey, et al Eric Potter Clarkson St. Mary's Court St. Mary's Gate Nottingham NG1 1LE / GB | Application number, filing date | 87305676.6 | 25.06.1987 | [1988/03] | Priority number, date | US19860886700 | 18.07.1986 Original published format: US 886700 | [1988/03] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0253530 | Date: | 20.01.1988 | Language: | EN | [1988/03] | Type: | A3 Search report | No.: | EP0253530 | Date: | 08.03.1989 | Language: | EN | [1989/10] | Type: | B1 Patent specification | No.: | EP0253530 | Date: | 09.10.1991 | Language: | EN | [1991/41] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 18.01.1989 | Classification | IPC: | H03K19/177 | [1988/03] | CPC: |
H03K19/17752 (EP,US);
H03K19/17704 (EP,US);
H03K19/1776 (EP,US)
| Designated contracting states | DE, FR, GB, IT [1988/03] | Title | German: | Dynamisch rekonfigurierbare Feldlogik | [1988/03] | English: | Dynamically reconfigurable array logic | [1988/03] | French: | Réseau logique reconfigurable dynamiquement | [1988/03] | Examination procedure | 21.08.1989 | Examination requested [1989/42] | 01.06.1990 | Despatch of a communication from the examining division (Time limit: M06) | 26.10.1990 | Reply to a communication from the examining division | 18.01.1991 | Despatch of communication of intention to grant (Approval: Yes) | 08.04.1991 | Communication of intention to grant the patent | 21.06.1991 | Fee for grant paid | 21.06.1991 | Fee for publishing/printing paid | Opposition(s) | 10.07.1992 | No opposition filed within time limit [1992/40] | Fees paid | Renewal fee | 13.03.1989 | Renewal fee patent year 03 | 20.03.1990 | Renewal fee patent year 04 | 18.03.1991 | Renewal fee patent year 05 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [Y]EP0055348 (IBM [US]); | [A]EP0173967 (HITACHI LTD [JP]) | [Y] - ELECTRONIC DESIGN, vol. 33, no. 25, October 1985, pages 123-128,130, Hasbrouck Heights, New Jersey, US; S. LANDRY: "Application-specific ICs, relying on RAM, implement almost any logic function" | [A] - PROCEEDINGS OF THE IEEE 1986 CUSTOM INTEGRATED CIRCUITS CONFERENCE, Rochester, New York, 12 - 15th May 1986, pages 233-235, IEEE; W.S CARTER et al.: "A user programmable reconfigurable logic array" | [A] - COMPUTER DESIGN, vol. 16, no. 1, January 1977, pages 98-101; S. WASER: "p/ROM card simplifies computer diagnosis" |