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Extract from the Register of European Patents

EP About this file: EP0282975

EP0282975 - Multi-stage integrated decoder device [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  13.08.1992
Database last updated on 15.06.2024
Most recent event   Tooltip13.08.1992No opposition filed within time limitpublished on 30.09.1992 [1992/40]
Applicant(s)For all designated states
Werner-von-Siemens-Str. 1
DE-80333 München / DE
Former [1988/38]For all designated states
Wittelsbacherplatz 2
D-80333 München / DE
Inventor(s)01 / Paul, Manfred, Dipl.-Ing.
Fichtenstrasse 18
D-8043 Unterföhring / DE
02 / Hoffmann, Kurt, Dr. Prof.
Nelkenweg 20
D-8028 Taufkirchen / DE
03 / Kowarik, Oskar, Dr. rer. nat.
Goethering 70
D-8018 Grafing / DE
04 / Kraus, Rainer, Dipl.-Phys.
Weidener Strasse 21
D-8000 München 83 / DE
Application number, filing date88104113.115.03.1988
Priority number, dateDE1987370852316.03.1987         Original published format: DE 3708523
DE1987370852516.03.1987         Original published format: DE 3708525
Filing languageDE
Procedural languageDE
PublicationType: A1 Application with search report 
Type: B1 Patent specification 
Search report(s)(Supplementary) European search report - dispatched on:EP13.07.1988
ClassificationIPC:G11C8/00, G11C29/00
G11C8/12 (EP,US); G11C29/34 (EP,US)
Designated contracting statesAT,   DE,   FR,   GB,   IT,   NL [1988/38]
TitleGerman:Mehrstufige integrierte Dekodereinrichtung[1988/38]
English:Multi-stage integrated decoder device[1988/38]
French:Dispositif intégré de décodeur à plusieurs étages[1988/38]
Examination procedure13.03.1989Examination requested  [1989/22]
14.01.1991Despatch of communication of intention to grant (Approval: Yes)
08.03.1991Communication of intention to grant the patent
27.05.1991Fee for grant paid
27.05.1991Fee for publishing/printing paid
Opposition(s)10.07.1992No opposition filed within time limit [1992/40]
Fees paidRenewal fee
28.03.1990Renewal fee patent year 03
20.12.1990Renewal fee patent year 04
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Documents cited:Search[A]EP0115187  (FUJITSU LTD [JP]);
 [A]EP0117903  (NEC CORP [JP]);
 [A]  - THE 10TH INTERNATIONAL SYMPOSIUM ON FAULT-TOLERANT COMPUTING, Digest of Papers FTCS-10, 1.-3. Oktober 1980, "Catalog" Nr. 80CH1604-8, Seiten 131-136, IEEE, New York, US; HONG et al.: "FITPLA: a programmable logic array for function independent testing"
 [A]  - IBM TECHNICAL DISCLOSURE BULLETIN, Band 27, Nr. 4B, September 1984, Seiten 2439-2441, New York, US; PROEBSTER et al.: "High-speed chip card reading"
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.