Extract from the Register of European Patents

About this file: EP0295646

EP0295646 - Arithmetic operation processing apparatus of the parallel processing type and compiler which is used in this apparatus [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  18.07.1997
Database last updated on 23.01.2020
Most recent event   Tooltip18.07.1997No opposition filed within time limitpublished on 03.09.1997 [1997/36]
Applicant(s)For all designated states
Hitachi, Ltd.
6, Kanda Surugadai 4-chome
Chiyoda-ku
Tokyo / JP
[N/P]
Former [1988/51]For all designated states
HITACHI, LTD.
6, Kanda Surugadai 4-chome
Chiyoda-ku, Tokyo 100 / JP
Inventor(s)01 / Kametani, Masatsugu
Niihariryo 3602, Shimoinayoshi
Chiyodamura Niihari-gun Ibaraki-ken / JP
[1988/51]
Representative(s)Beetz & Partner mbB
Patentanwälte
Robert-Koch-Str. 1
80538 München / DE
[N/P]
Former [1988/51]Patentanwälte Beetz - Timpe - Siegfried Schmitt-Fumian - Mayr
Steinsdorfstrasse 10
D-80538 München / DE
Application number, filing date88109533.515.06.1988
[1988/51]
Priority number, dateJP1987015120719.06.1987         Original published format: JP 15120787
JP1987016533803.07.1987         Original published format: JP 16533887
[1988/51]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0295646
Date:21.12.1988
Language:EN
[1988/51]
Type: A3 Search report 
No.:EP0295646
Date:12.02.1992
Language:EN
[1992/07]
Type: B1 Patent specification 
No.:EP0295646
Date:11.09.1996
Language:EN
[1996/37]
Search report(s)(Supplementary) European search report - dispatched on:EP19.12.1991
ClassificationInternational:G06F9/38, G06F9/44
[1996/37]
Former International [1988/51]G06F9/44, G06F9/38
Designated contracting statesDE,   FR,   GB [1988/51]
TitleGerman:Arithmetik-Parallelverarbeitungseinheit und zugehöriger Kompilator[1988/51]
English:Arithmetic operation processing apparatus of the parallel processing type and compiler which is used in this apparatus[1988/51]
French:Unité arithmétique de traitement parallèle et compilateur associé[1988/51]
Examination procedure14.11.1990Examination requested  [1991/02]
30.09.1994Despatch of a communication from the examining division (Time limit: M07)
09.05.1995Reply to a communication from the examining division
14.11.1995Despatch of communication of intention to grant (Approval: Yes)
14.03.1996Communication of intention to grant the patent
07.06.1996Fee for grant paid
07.06.1996Fee for publishing/printing paid
Opposition(s)12.06.1997No opposition filed within time limit [1997/36]
Fees paidRenewal fee
25.06.1990Renewal fee patent year 03
25.06.1991Renewal fee patent year 04
22.06.1992Renewal fee patent year 05
29.06.1993Renewal fee patent year 06
30.06.1994Renewal fee patent year 07
29.06.1995Renewal fee patent year 08
28.06.1996Renewal fee patent year 09
Documents cited:Search[A]EP0092429  ;
 [A]US4367524
 [A]  - COMPUTER DESIGN vol. 24, no. 15, November 1985, LITTLETON,MASSACHUSETTS, USA pages 30 - 31; T. WILLIAMS: 'Parallel architecture targets scientific math operations'
 [A]  - IEEE ELECTRO vol. 8, no. 6/3, 1983, NEW YORK, USA pages 1 - 10; R. C. HAUSMAN ET AL.: 'ST-100 Array Processor Architectural Highlights'