Extract from the Register of European Patents

About this file: EP0343968

EP0343968 - Programmable logic device [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  03.01.1996
Database last updated on 28.01.2020
Most recent event   Tooltip03.01.1996No opposition filed within time limitpublished on 24.01.1996 [1996/04]
Applicant(s)For all designated states
FUJITSU LIMITED
1015, Kamikodanaka, Nakahara-ku Kawasaki-shi
Kanagawa 211 / JP
For all designated states
FUJITSU VLSI LIMITED
1844-2, Kozoji-cho 2-chome Kasugai-shi
Aichi 487 / JP
[N/P]
Former [1989/48]For all designated states
FUJITSU LIMITED
1015, Kamikodanaka, Nakahara-ku
Kawasaki-shi, Kanagawa 211 / JP
For all designated states
FUJITSU VLSI LIMITED
1844-2, Kozoji-cho 2-chome
Kasugai-shi Aichi 487 / JP
Inventor(s)01 / Higuchi, Mitsuo
Haitsu Nakamachi 201 2-22-5, Nakamachi
Meguro-ku Tokyo 153 / JP
02 / Ogura, Kiyonori
Satsuki Mansyon 102 2-17-17, Suge Tama-ku
Kawasaki-shi Kanagawa 214 / JP
03 / Shimbayashi, Kohji
Kopo Painari 202 3-5-1 Kita Kozoji-cho
Kasugai-shi Aichi 487 / JP
04 / Nakaoka, Yasuhiro
Yukimi-so 972, Kashimada Saiwai-ku
Kawasaki-shi Kanagawa 211 / JP
[1989/48]
Representative(s)Rackham, Stephen Neil , et al
Gill Jennings & Every LLP Broadgate House 7 Eldon Street
London EC2M 7LH / GB
[N/P]
Former [1989/48]Rackham, Stephen Neil , et al
GILL JENNINGS & EVERY, Broadgate House, 7 Eldon Street
London EC2M 7LH / GB
Application number, filing date89305267.024.05.1989
[1989/48]
Priority number, dateJP1988012601425.05.1988         Original published format: JP 12601488
[1989/48]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0343968
Date:29.11.1989
Language:EN
[1989/48]
Type: A3 Search report 
No.:EP0343968
Date:31.10.1990
Language:EN
[1990/44]
Type: B1 Patent specification 
No.:EP0343968
Date:01.02.1995
Language:EN
[1995/05]
Search report(s)(Supplementary) European search report - dispatched on:EP10.09.1990
ClassificationInternational:H03K19/177
[1989/48]
Designated contracting statesDE,   FR,   GB [1989/48]
TitleGerman:Programmierbare Logik-Vorrichtung[1989/48]
English:Programmable logic device[1989/48]
French:Dispositif logique programmable[1989/48]
Examination procedure28.12.1990Examination requested  [1991/10]
19.10.1992Despatch of a communication from the examining division (Time limit: M08)
27.04.1993Reply to a communication from the examining division
24.09.1993Despatch of a communication from the examining division (Time limit: M04)
23.12.1993Reply to a communication from the examining division
28.03.1994Despatch of communication of intention to grant (Approval: Yes)
05.08.1994Communication of intention to grant the patent
28.10.1994Fee for grant paid
28.10.1994Fee for publishing/printing paid
Opposition(s)03.11.1995No opposition filed within time limit [1996/04]
Fees paidRenewal fee
17.05.1991Renewal fee patent year 03
11.05.1992Renewal fee patent year 04
10.05.1993Renewal fee patent year 05
09.05.1994Renewal fee patent year 06
Documents cited:Search[X]US4422072  (CAVLAN NAPOLEONE [US]);
 [X]EP0227329  (ADVANCED MICRO DEVICES INC [US]);
 [X]EP0055348  (IBM [US]);
 [A]WO8600165  (ALTERA CORP [US])
 [A]  - WESCON/87
 [A]  - ELECTRONIC DESIGN
ExaminationEP0307912
    - WESCON/87, vol. 31, 1987, pages 1-11, Los Angeles, US; O.P. AGRAWAL: "AMD/MMI's Spectrum of Application Specific PLDs"
    - ELECTRONIC DESIGN, vol. 35, no. 8, April 1987, pages 13-25, Has- brouck Heights, NJ, US; D. BURSKY: "Faster, more complex PLDs arrive with better programming tools"