Extract from the Register of European Patents

About this file: EP0507567

EP0507567 - Field effect transistor structure and method of fabrication [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  05.06.1998
Database last updated on 18.01.2020
Most recent event   Tooltip05.06.1998No opposition filed within time limitpublished on 22.07.1998 [1998/30]
Applicant(s)For all designated states
STMicroelectronics, Inc.
1310 Electronics Drive
Carrollton, TX 75006-5039 / US
[N/P]
Former [1992/41]For all designated states
SGS-THOMSON MICROELECTRONICS, INC.
1310 Electronics Drive
Carrollton Texas 75006 / US
Inventor(s)01 / Mehdi, Zamanian
2021 Hearthstone
Carrollton, Texas 75001 / US
[1992/41]
Representative(s)Palmer, Roger , et al
PAGE, WHITE & FARRER 54 Doughty Street
London WC1N 2LS / GB
[1992/41]
Application number, filing date92302866.601.04.1992
[1992/41]
Priority number, dateUS1991067801801.04.1991         Original published format: US 678018
[1992/41]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0507567
Date:07.10.1992
Language:EN
[1992/41]
Type: A3 Search report 
No.:EP0507567
Date:21.04.1993
Language:EN
[1993/16]
Type: B1 Patent specification 
No.:EP0507567
Date:30.07.1997
Language:EN
[1997/31]
Search report(s)(Supplementary) European search report - dispatched on:EP03.03.1993
ClassificationInternational:H01L29/772, H01L21/336, H01L29/08
[1997/31]
Former International [1993/16]H01L29/784, H01L21/336, H01L29/08
Former International [1992/41]H01L29/784, H01L21/336
Designated contracting statesDE,   FR,   GB,   IT [1992/41]
TitleGerman:Feldeffekttransistorstruktur und Verfahren zur Herstellung[1992/41]
English:Field effect transistor structure and method of fabrication[1992/41]
French:Structure de transistor à effet de champ et méthode de fabrication[1992/41]
Examination procedure05.10.1993Examination requested  [1993/49]
20.03.1995Despatch of a communication from the examining division (Time limit: M06)
28.09.1995Reply to a communication from the examining division
11.01.1996Despatch of a communication from the examining division (Time limit: M06)
19.07.1996Reply to a communication from the examining division
03.09.1996Despatch of communication of intention to grant (Approval: No)
15.01.1997Despatch of communication of intention to grant (Approval: later approval)
31.01.1997Communication of intention to grant the patent
21.04.1997Fee for grant paid
21.04.1997Fee for publishing/printing paid
Opposition(s)05.05.1998No opposition filed within time limit [1998/30]
Fees paidRenewal fee
10.03.1994Renewal fee patent year 03
28.03.1995Renewal fee patent year 04
24.04.1996Renewal fee patent year 05
23.04.1997Renewal fee patent year 06
Documents cited:Search[Y]EP0187016  (TOSHIBA KK [JP]);
 [Y]EP0322886  (TOSHIBA KK [JP]);
 [A]EP0193117  (TOSHIBA KK [JP])
 [A]  - PFIESTER J. R., "SURFACE-GRADED LDD MOSFET.", MOTOROLA TECHNICAL DEVELOPMENTS., MOTOROLA INC. SCHAUMBURG, ILLINOIS., US, US, (19890801), vol. 9., ISSN 0887-5286, page 01/02., XP000053758
by applicantUS4356623