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Extract from the Register of European Patents

EP About this file: EP0547240

EP0547240 - RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING FAST TRAP AND EXCEPTION STATE [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  10.11.2000
Database last updated on 18.05.2024
Most recent event   Tooltip07.12.2007Lapse of the patent in a contracting state
New state(s): IT
published on 09.01.2008  [2008/02]
Applicant(s)For all designated states
Seiko Epson Corporation
4-1, Nishi-Shinjuku 2-chome
Shinjuku-ku
Tokyo 163-0811 / JP
[N/P]
Former [2000/02]For all designated states
SEIKO EPSON CORPORATION
4-1, Nishishinjuku 2-chome
Shinjuku-ku, Tokyo 163-0811 / JP
Former [1993/25]For all designated states
SEIKO EPSON CORPORATION
4-1, Nishishinjuku 2-chome
Shinjuku-ku Tokyo 163 / JP
Inventor(s)01 / NGUYEN, Le Trong
15096 Danielle Place
Monte Sereno, CA 95030 / US
02 / LENTZ, Derek, J.
17400 Phillips Avenue
Los Gatos, CA 95032 / US
03 / MIYAYAMA, Yoshiyuki
2171 Rancho McCormick Boulevard
Santa Clara, CA 95050 / US
04 / GARG, Sanjiv
46820 Sentinel Drive
Freemont, CA 94539 / US
05 / HAGIWARA, Yasuaki
2250 Monroe Street Apt. 274
Santa Clara, CA 95050 / US
06 / WANG, Johannes
25 King Street
Redwood City, CA 94062 / US
07 / TRANG, Quang, H.
2045 Mayfield Avenue
San Jose, CA 95130 / US
[1993/25]
Representative(s)Grünecker Patent- und Rechtsanwälte PartG mbB
Leopoldstraße 4
80802 München / DE
[N/P]
Former [1993/25]Grünecker, Kinkeldey, Stockmair & Schwanhäusser Anwaltssozietät
Maximilianstrasse 58
D-80538 München / DE
Application number, filing date92914386.507.07.1992
[1993/25]
WO1992JP00872
Priority number, dateUS1991072694208.07.1991         Original published format: US 726942
[1993/25]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report
No.:WO9301547
Date:21.01.1993
Language:EN
[1993/03]
Type: A1 Application with search report 
No.:EP0547240
Date:23.06.1993
Language:EN
The application published by WIPO in one of the EPO official languages on 21.01.1993 takes the place of the publication of the European patent application.
[1993/25]
Type: B1 Patent specification 
No.:EP0547240
Date:12.01.2000
Language:EN
[2000/02]
Search report(s)International search report - published on:EP21.01.1993
ClassificationIPC:G06F9/38
[1993/25]
CPC:
G06F9/3865 (EP,KR,US); G06F9/3814 (EP,KR,US); G06F15/7842 (EP,KR,US);
G06F9/3017 (EP,KR,US); G06F9/32 (EP,US); G06F9/322 (EP,KR,US);
G06F9/3802 (EP,US); G06F9/3804 (EP,KR,US); G06F9/3836 (EP,US);
G06F9/384 (EP,KR,US); G06F9/3858 (EP,KR,US); G06F9/3861 (EP,US);
G06F9/3885 (EP,KR,US); G06F9/462 (EP,KR,US); G06F9/4812 (EP,KR,US) (-)
Designated contracting statesAT,   BE,   CH,   DE,   DK,   ES,   FR,   GB,   GR,   IT,   LI,   LU,   MC,   NL,   SE [1993/25]
TitleGerman:RISC-MIKROPROZESSORARCHITEKTUR MIT SCHNELLEM UNTERBRECHUNGS- UND AUSNAHMEMODUS[1993/25]
English:RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING FAST TRAP AND EXCEPTION STATE[1993/25]
French:ARCHITECTURE RISC DE MICROPROCESSEUR AVEC MODE D'INTERRUPTION ET D'EXCEPTION RAPIDE[1993/25]
Entry into regional phase24.02.1993National basic fee paid 
24.02.1993Designation fee(s) paid 
20.07.1993Examination fee paid 
Examination procedure20.07.1993Examination requested  [1993/37]
21.03.1997Despatch of a communication from the examining division (Time limit: M04)
28.07.1997Reply to a communication from the examining division
13.03.1998Despatch of a communication from the examining division (Time limit: M04)
14.05.1998Reply to a communication from the examining division
23.02.1999Despatch of communication of intention to grant (Approval: Yes)
13.07.1999Communication of intention to grant the patent
11.10.1999Fee for grant paid
11.10.1999Fee for publishing/printing paid
Divisional application(s)EP99112833.1  / EP0945787
Opposition(s)13.10.2000No opposition filed within time limit [2000/52]
Fees paidRenewal fee
29.07.1994Renewal fee patent year 03
31.07.1995Renewal fee patent year 04
31.07.1996Renewal fee patent year 05
30.07.1997Renewal fee patent year 06
29.07.1998Renewal fee patent year 07
29.07.1999Renewal fee patent year 08
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipAT12.01.2000
BE12.01.2000
CH12.01.2000
ES12.01.2000
GR12.01.2000
IT12.01.2000
LI12.01.2000
NL12.01.2000
SE12.01.2000
DK12.04.2000
LU07.07.2000
MC31.07.2000
[2008/02]
Former [2004/39]AT12.01.2000
BE12.01.2000
CH12.01.2000
ES12.01.2000
GR12.01.2000
LI12.01.2000
NL12.01.2000
SE12.01.2000
DK12.04.2000
LU07.07.2000
MC31.07.2000
Former [2004/07]AT12.01.2000
BE12.01.2000
CH12.01.2000
ES12.01.2000
GR12.01.2000
LI12.01.2000
NL12.01.2000
SE12.01.2000
DK12.04.2000
MC31.07.2000
Former [2003/45]AT12.01.2000
BE12.01.2000
CH12.01.2000
ES12.01.2000
LI12.01.2000
NL12.01.2000
SE12.01.2000
DK12.04.2000
MC31.07.2000
Former [2003/07]AT12.01.2000
BE12.01.2000
CH12.01.2000
ES12.01.2000
LI12.01.2000
NL12.01.2000
SE12.01.2000
MC31.07.2000
Former [2002/42]AT12.01.2000
BE12.01.2000
CH12.01.2000
ES12.01.2000
LI12.01.2000
SE12.01.2000
MC31.07.2000
Former [2002/25]AT12.01.2000
BE12.01.2000
CH12.01.2000
ES12.01.2000
LI12.01.2000
SE12.01.2000
Former [2002/23]AT12.01.2000
BE12.01.2000
CH12.01.2000
LI12.01.2000
SE12.01.2000
Former [2001/08]AT12.01.2000
BE12.01.2000
CH12.01.2000
LI12.01.2000
Former [2000/52]CH12.01.2000
LI12.01.2000
Former [2000/50]CH17.04.2000
LI17.04.2000
Cited inInternational search[Y]JP60225943  ;
 [A]US4296470  (FAIRCHILD PETER T, et al);
 [X]US4410939  (KAWAKAMI KATSURA [JP]);
 [X]US4434461  (PUHL LARRY C [US]);
 [X]US4459657  (MURAO YUTAKA [JP]);
 [Y]EP0372751  (INT COMPUTERS LTD [GB]);
 [A]EP0377991  (IBM [US]);
 [A]EP0402856  (NEC CORP [JP]);
 [A]US5003462  (BLANER BARTHOLOMEW [US], et al);
 [X]  - MELEAR C., "THE DESIGN OF THE 88000 RISC FAMILY.", IEEE MICRO., IEEE SERVICE CENTER, LOS ALAMITOS, CA., US, US, (19890401), vol. 09., no. 02., doi:10.1109/40.24848, ISSN 0272-1732, pages 26 - 38., XP000124913

DOI:   http://dx.doi.org/10.1109/40.24848
 [Y]  - PATENT ABSTRACTS OF JAPAN vol. 010, no. 089 (P-444)8 April 1986 & JP,A,60 225 943 ( HITACHI SEISAKUSHO K K ) 11 November 1985, & JP60225943 A 19851111
 [Y]  - SMITH J. E., PLESZKUN A. R., "IMPLEMENTING PRECISE INTERRUPTS IN PIPELINED PROCESSORS.", IEEE TRANSACTIONS ON COMPUTERS., IEEE SERVICE CENTER, LOS ALAMITOS, CA., US, US, (19880501), vol. 37., no. 5., doi:10.1109/12.4607, ISSN 0018-9340, pages 562 - 573., XP000047779

DOI:   http://dx.doi.org/10.1109/12.4607
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.