Extract from the Register of European Patents

About this file: EP0660227

EP0660227 - Three input arithmetic logic unit forming the sum of a first and a second boolean combination of the inputs [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  07.03.2003
Database last updated on 19.08.2019
Most recent event   Tooltip07.03.2003No opposition filed within time limitpublished on 23.04.2003  [2003/17]
Applicant(s)For all designated states
Texas Instruments Incorporated
13500 North Central Expressway
Dallas, Texas 75265 / US
[N/P]
Former [1995/26]For all designated states
TEXAS INSTRUMENTS INCORPORATED
13500 North Central Expressway
Dallas Texas 75265 / US
Inventor(s)01 / Guttag, Karl M.
4015 South Sandy Court
Missouri City, Texas 77459 / US
02 / Simpson, Richard
21 The Marsh, Carlton
Bedford, MK43 7JU / GB
03 / Walsh, Brendan
14, Chillingham Green
Bedford, MK41 8HT / GB
 [2001/48]
Former [1995/26]01 / Guttag, Karl M.
4015 South Sandy Court
Missouri City, Rexas 77459 / US
02 / Simpson, Richard
21 The Marsh, Carlton
Bedford, MK43 7JU / US
03 / Walsh, Brendan
14, Chillingham Green
Bedford, MK41 8HT / GB
Representative(s)Legg, Cyrus James Grahame , et al
Abel & Imray
20 Red Lion Street
London WC1R 4PQ / GB
[N/P]
Former [2000/20]Legg, Cyrus James Grahame , et al
ABEL & IMRAY, 20 Red Lion Street
London WC1R 4PQ / GB
Former [1995/26]Blanco White, Henry Nicholas , et al
ABEL & IMRAY Northumberland House 303-306 High Holborn
London WC1V 7LH / GB
Application number, filing date94308888.030.11.1994
[1995/26]
Priority number, dateUS1993016011330.11.1993         Original published format: US 160113
[1995/26]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0660227
Date:28.06.1995
Language:EN
[1995/26]
Type: A3 Search report 
No.:EP0660227
Date:24.01.1996
[1996/04]
Type: B1 Patent specification 
No.:EP0660227
Date:02.05.2002
Language:EN
[2002/18]
Search report(s)(Supplementary) European search report - dispatched on:EP08.12.1995
ClassificationInternational:G06F7/48
[1995/26]
Designated contracting statesDE,   FR,   GB,   IT,   NL [1995/26]
TitleGerman:Arithmetisch-logische Einheit mit drei Eingängen, die die Summe einer ersten und einer zweiten booleschen Kombination berechnet[1995/26]
English:Three input arithmetic logic unit forming the sum of a first and a second boolean combination of the inputs[1995/26]
French:Unité arithmetique et logique à trois entrées calculant la somme d'un premier et une seconde combinaison booléenne des entrées[1995/26]
Examination procedure18.07.1996Examination requested  [1996/37]
17.05.1999Despatch of a communication from the examining division (Time limit: M06)
17.03.2000Reply to a communication from the examining division
23.06.2000Despatch of a communication from the examining division (Time limit: M06)
02.04.2001Reply to a communication from the examining division
30.05.2001Despatch of communication of intention to grant (Approval: Yes)
11.10.2001Communication of intention to grant the patent
08.01.2002Fee for grant paid
08.01.2002Fee for publishing/printing paid
Opposition(s)04.02.2003No opposition filed within time limit [2003/17]
Request for further processing for:02.04.2001Request for further processing filed
29.03.2001Full payment received (date of receipt of payment)
Request granted
11.04.2001Decision despatched
17.03.2000Request for further processing filed
16.03.2000Full payment received (date of receipt of payment)
Request granted
30.03.2000Decision despatched
Fees paidRenewal fee
11.11.1996Renewal fee patent year 03
10.11.1997Renewal fee patent year 04
10.11.1998Renewal fee patent year 05
12.11.1999Renewal fee patent year 06
27.02.2001Renewal fee patent year 07
12.02.2002Renewal fee patent year 08
Penalty fee
Additional fee for renewal fee
30.11.200007   M06   Fee paid on   27.02.2001
30.11.200108   M06   Fee paid on   12.02.2002
Lapses during opposition  TooltipNL02.05.2002
[2003/08]
Documents cited:Search[A]EP0395958  (HITACHI LTD [JP]) [A] 1 * column 12, line 23 - line 41; figure 6 *;
 [A]US4601055  (KENT ERNEST W [US]) [A] 1 * column 12, line 12 - line 34; figure 6 *;
 [A]EP0451562  (IBM [US]) [A] 1 * page 11, line 19 - page 12, line 2; figure 9 *;
 [A]  VORSTERMANS ET AL, "An image processor for a multi image processing system", MICROPROCESSING AND MICROPROGRAMMING, AMSTERDAM NL, vol. 18, no. 1-5, doi:doi:10.1016/0165-6074(86)90088-8, pages 525 - 538, XP024232120 [A] 1 * paragraph [03.2]; figures 3,5,9 *

DOI:   http://dx.doi.org/10.1016/0165-6074(86)90088-8