Extract from the Register of European Patents

About this file: EP0681326

EP0681326 - Semi-conductor device and method of manufacturing the same [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  30.04.2004
Database last updated on 13.07.2018
Most recent event   Tooltip30.04.2004No opposition filed within time limitpublished on 16.06.2004  [2004/25]
Applicant(s)For all designated states
NGK Insulators, Ltd.
2-56, Suda-Cho, Mizuho-ku
Nagoya City, Aichi Pref. / JP
[N/P]
Former [1995/45]For all designated states
NGK INSULATORS, LTD.
2-56, Suda-cho, Mizuho-ku
Nagoya City Aichi Pref. / JP
Inventor(s)01 / Terasawa, Yoshio
622-19 Ichige
Katsuta City, Ibaraki Pref. / JP
[1995/45]
Representative(s)Paget, Hugh Charles Edward , et al
Mewburn Ellis LLP
City Tower
40 Basinghall Street
London EC2V 5DE / GB
[N/P]
Former [1995/45]Paget, Hugh Charles Edward , et al
MEWBURN ELLIS York House 23 Kingsway
London WC2B 6HP / GB
Application number, filing date95302799.226.04.1995
[1995/45]
Priority number, dateJP1994009235128.04.1994         Original published format: JP 9235194
[1995/45]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0681326
Date:08.11.1995
Language:EN
[1995/45]
Type: A3 Search report 
No.:EP0681326
Date:13.05.1998
[1998/20]
Type: B1 Patent specification 
No.:EP0681326
Date:25.06.2003
Language:EN
[2003/26]
Search report(s)(Supplementary) European search report - dispatched on:EP26.03.1998
ClassificationInternational:H01L21/8248, H01L29/745
[1995/45]
Designated contracting statesCH,   DE,   GB,   LI,   SE [1995/45]
TitleGerman:Halbleitervorrichtung und Verfahren zu deren Herstellung[1995/45]
English:Semi-conductor device and method of manufacturing the same[1995/45]
French:Dispositif semi-conducteur et procédé pour fabriquer celui-ci[1995/45]
Examination procedure24.09.1998Examination requested  [1998/48]
17.01.2002Despatch of a communication from the examining division (Time limit: M06)
23.07.2002Reply to a communication from the examining division
05.12.2002Communication of intention to grant the patent
31.03.2003Fee for grant paid
31.03.2003Fee for publishing/printing paid
Opposition(s)26.03.2004No opposition filed within time limit [2004/25]
Fees paidRenewal fee
23.04.1997Renewal fee patent year 03
21.04.1998Renewal fee patent year 04
21.04.1999Renewal fee patent year 05
27.04.2000Renewal fee patent year 06
24.04.2001Renewal fee patent year 07
23.04.2002Renewal fee patent year 08
23.04.2003Renewal fee patent year 09
Documents cited:Search[XY]US4528745  (MURAOKA KIMIHIRO [JP]) [X] 1,4,5,7,8 * column 1, line 42 - line 47 * * column 2, line 20 - line 26 * * column 3, line 49 - column 4, line 18; figure 3C * [Y] 2,3,6;
 [Y]US4974061  (TORIKAI TOSHITAKA [JP]) [Y] 2,3,6 * column 4, line 34 - line 45; figure 2; claims 1,2 *;
 [A]US5153695  (GOBRECHT JENS [CH], et al) [A] 1,4,5,7,8 * column 6, line 48 - column 7, line 50; figure 5B *;
 [A]EP0014080  (HITACHI LTD [JP]) [A] 1,5 * page 15, line 8 - page 16, line 1; figure 5 *
Examination   STANLEY WOLF, Silicon processing in the VLSI era, vol. 2: Process integration, SUNSET BEACH, CA, LATTICE PRESS,