Extract from the Register of European Patents

About this file: EP0774788

EP0774788 - A PMOS flash memory cell capable of multi-level threshold voltage storage [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  07.06.2002
Database last updated on 20.08.2019
Most recent event   Tooltip04.01.2008Lapse of the patent in a contracting state
New state(s): IT
published on 06.02.2008  [2008/06]
Applicant(s)For all designated states
Programmable Microelectronics Corporation
1350 Ridder Park Drive San Jose
California 95131 / US
[N/P]
Former [1997/21]For all designated states
Programmable Microelectronics Corporation
1350 Ridder Park Drive
San Jose, California 95131 / US
Inventor(s)01 / Chang, Shang-De T.
43570 Southerland Way
Fremont, California 94539 / US
[1997/21]
Representative(s)Atkinson, Ralph , et al
Atkinson & Company
Intellectual Property Limited
7 Moorgate Road
Rotherham South Yorkshire S60 2BF / GB
[N/P]
Former [1997/21]Atkinson, Ralph , et al
Atkinson & Co., The Technology Park, 60 Shirland Lane
Sheffield S9 3SP / GB
Application number, filing date96307875.330.10.1996
[1997/21]
Priority number, dateUS1995057751414.11.1995         Original published format: US 577514
[1997/21]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report 
No.:EP0774788
Date:21.05.1997
Language:EN
[1997/21]
Type: B1 Patent specification 
No.:EP0774788
Date:01.08.2001
Language:EN
[2001/31]
Search report(s)(Supplementary) European search report - dispatched on:EP13.03.1997
ClassificationInternational:H01L29/788, H01L27/115, G11C16/04
[1997/21]
Designated contracting statesAT,   BE,   DE,   FI,   FR,   GB,   IT,   NL,   SE [1997/21]
TitleGerman:PMOS-Flash-Speicherzelle mit mehrstufiger Schwellspannung[1997/21]
English:A PMOS flash memory cell capable of multi-level threshold voltage storage[1997/21]
French:Cellule mémoire PMOS flash pouvant avoir plusieurs niveaux de tension de seuil[1997/21]
Examination procedure07.07.1997Examination requested  [1997/37]
13.02.1998Despatch of a communication from the examining division (Time limit: M06)
15.06.1998Reply to a communication from the examining division
23.02.1999Despatch of a communication from the examining division (Time limit: M04)
23.06.1999Reply to a communication from the examining division
18.08.2000Despatch of communication of intention to grant (Approval: Yes)
29.01.2001Communication of intention to grant the patent
26.04.2001Fee for grant paid
26.04.2001Fee for publishing/printing paid
Opposition(s)03.05.2002No opposition filed within time limit [2002/30]
Fees paidRenewal fee
05.10.1998Renewal fee patent year 03
04.10.1999Renewal fee patent year 04
04.10.2000Renewal fee patent year 05
Lapses during opposition  TooltipAT01.08.2001
BE01.08.2001
FI01.08.2001
FR01.08.2001
IT01.08.2001
NL01.08.2001
SE01.11.2001
DE03.11.2001
[2008/06]
Former [2006/14]AT01.08.2001
BE01.08.2001
FI01.08.2001
FR01.08.2001
NL01.08.2001
SE01.11.2001
DE03.11.2001
Former [2003/17]AT01.08.2001
BE01.08.2001
FI01.08.2001
NL01.08.2001
SE01.11.2001
DE03.11.2001
FR28.12.2001
Former [2003/09]AT01.08.2001
BE01.08.2001
FI01.08.2001
NL01.08.2001
SE01.11.2001
FR28.12.2001
Former [2002/29]AT01.08.2001
BE01.08.2001
FI01.08.2001
SE01.11.2001
FR28.12.2001
Former [2002/20]AT01.08.2001
FI01.08.2001
SE01.11.2001
FR28.12.2001
Former [2002/18]AT01.08.2001
FI01.08.2001
FR28.12.2001
Former [2002/15]AT01.08.2001
FI01.08.2001
Documents cited:Search[A]EP0255489  (SGS MICROELETTRONICA SPA [IT]) [A] 1,2,4,19 * column W *;
 [A]US4953928  (ANDERSON JANEEN D W [US], et al) [A] 1 * column W *;
 [A]EP0618621  (TOSHIBA KK [JP]) [A] 4-18 * column W *
 [A]  A.J. MONTALVO ET AL., "Improved floating-gate devices using standard CMOS technology", IEEE ELECTRON DEVICE LETTERS, NEW YORK US, (199308), vol. 14, no. 8, pages 372 - 374, XP000418574 [A] 1 * the whole document *

DOI:   http://dx.doi.org/10.1109/55.225583
 [A]  "High-speed, low-power/low-voltage P-channel NVRAM using channel-hot-carrier programming and tunneling erase through silicon-rich oxide", IBM TECHNICAL DISCLOSURE BULLETIN, NEW YORK US, (199210), vol. 35, no. 5, pages 339 - 340, XP000312997 [A] 1,2 * the whole document *