Extract from the Register of European Patents

About this file: EP0834124

EP0834124 - PARALLEL TESTING OF CPU CACHE AND INSTRUCTION UNITS [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  19.07.2002
Database last updated on 24.04.2019
Most recent event   Tooltip19.07.2002No opposition filed within time limitpublished on 04.09.2002  [2002/36]
Applicant(s)For all designated states
Elonex plc
2 Apsley Way
London NW2 7LF / GB
[1998/52]
Former [1998/15]For all designated states
Elonex Software Solutions, Inc.
4th floor, 100 South Ellsworth Avenue
San Mateo, CA 94401 / US
Inventor(s)01 / KIKINIS, Dan
20264 Ljepava Drive
Saratoga, CA 95070 / US
[1998/15]
Representative(s)Freed, Arthur Woolf , et al
Marks & Clerk Incorporating Edward Evans Barker 90 Long Acre
London WC2E 9RA / GB
[N/P]
Former [1998/15]Freed, Arthur Woolf , et al
Reginald W. Barker & Co., Chancery House, 53-64, Chancery Lane
London, WC2A 1QU / GB
Application number, filing date96921674.617.06.1996
[1998/15]
WO1996US10516
Priority number, dateUS1995049115716.06.1995         Original published format: US 491157
[1998/15]
Filing languageEN
Procedural languageEN
PublicationType: A1  Application with search report
No.:WO9700478
Date:03.01.1997
Language:EN
[1997/02]
Type: A1 Application with search report 
No.:EP0834124
Date:08.04.1998
Language:EN
The application has been published by WIPO in one of the EPO official languages on 03.01.1997
[1998/15]
Type: B1 Patent specification 
No.:EP0834124
Date:12.09.2001
Language:EN
[2001/37]
Search report(s)International search report - published on:US03.01.1997
(Supplementary) European search report - dispatched on:EP03.03.2000
ClassificationInternational:G06F11/00, G06F11/30, G11C29/00, G06F11/267, G06F11/273
[2000/16]
Former International [1998/15]G06F11/00, G06F11/30
Designated contracting statesAT,   CH,   DE,   FR,   GB,   LI,   NL [1998/15]
TitleGerman:PARALLELE PRÜFUNG EINES CPU-CACHESPEICHERS SOWIE BEFEHLSEINHEIT[1998/15]
English:PARALLEL TESTING OF CPU CACHE AND INSTRUCTION UNITS[1998/15]
French:CONTROLE PARALLELE D'UNE ANTEMEMOIRE DE PROCESSEUR CENTRAL ET D'UNITES D'INSTRUCTIONS[1998/15]
Entry into regional phase09.12.1997National basic fee paid 
09.12.1997Search fee paid 
09.12.1997Designation fee(s) paid 
09.12.1997Examination fee paid 
Examination procedure15.01.1997Request for preliminary examination filed
International Preliminary Examining Authority: US
09.12.1997Examination requested  [1998/15]
09.11.2000Despatch of communication of intention to grant (Approval: Yes)
04.01.2001Communication of intention to grant the patent
05.01.2001Fee for grant paid
05.01.2001Fee for publishing/printing paid
Opposition(s)13.06.2002No opposition filed within time limit [2002/36]
Fees paidRenewal fee
15.06.1998Renewal fee patent year 03
14.06.1999Renewal fee patent year 04
13.06.2000Renewal fee patent year 05
13.06.2001Renewal fee patent year 06
Documents cited:Search[A]  BHAVSAR D K ET AL, "TESTABILITY STRATEGY OF THE ALPHA AXP 21164 MICROPROCESSOR", PROCEEDINGS OF THE INTERNATIONAL TEST CONFERENCE,US,NEW YORK, IEEE, (1994), ISBN 0-7803-2103-0, pages 50 - 59, XP000519963 [A] 1-5 * page 51, column R, line 44 - page 52, column L, line 18; figure 1 * * page 53, column R, lines 15-19 *
International search[A]US5155844  (CHENG CHINGSHUN [US], et al);
 [A]US4891811  (ASH KEVIN J [US], et al);
 [A]US5398325  (CHANG JUNG-HERNG [US], et al);
 [A]US4553201  (POLLACK JR FRANK S [US]);
 [AP]US5479413  (SICOLA STEPHEN J [US], et al)