Extract from the Register of European Patents

About this file: EP0789398

EP0789398 - Semiconductor device having power MOS transistor including parasitic transistor [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  04.07.2008
Database last updated on 25.04.2019
Most recent event   Tooltip19.06.2009Lapse of the patent in a contracting statepublished on 22.07.2009  [2009/30]
Applicant(s)For all designated states
NEC Electronics Corporation
1753 Shimonumabe Nakahara-ku
Kawasaki, Kanagawa 211-8668 / JP
[2007/35]
Former [2003/19]For all designated states
NEC Electronics Corporation
1753 Shimonumabe, Nakahara-ku
Kawasaki, Kanagawa 211-8668 / JP
Former [1997/33]For all designated states
NEC CORPORATION
7-1, Shiba 5-chome Minato-ku
Tokyo / JP
Inventor(s)01 / Ohashi, Ikuo
NEC Corporation, 7-1, Shiba 5-chome
Minato-ku, Tokyo / JP
[1997/33]
Representative(s)Betten & Resch
Patent- und Rechtsanwälte PartGmbB
Postfach 10 02 51
80076 München / DE
[N/P]
Former [1997/33]Betten & Resch
Reichenbachstrasse 19
80469 München / DE
Application number, filing date97101895.706.02.1997
[1997/33]
Priority number, dateJP1996002015906.02.1996         Original published format: JP 2015996
[1997/33]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0789398
Date:13.08.1997
Language:EN
[1997/33]
Type: A3 Search report 
No.:EP0789398
Date:23.02.2000
[2000/08]
Type: B1 Patent specification 
No.:EP0789398
Date:29.08.2007
Language:EN
[2007/35]
Search report(s)(Supplementary) European search report - dispatched on:EP11.01.2000
ClassificationInternational:H01L27/02
[1997/33]
Designated contracting statesDE,   FR,   GB [1997/33]
TitleGerman:Halbleiteranordnung mit einem einen parasitären Transistor beinhaltenden MOS-Leistungstransistor[1997/33]
English:Semiconductor device having power MOS transistor including parasitic transistor[1997/33]
French:Dispositif semi-conducteur comprenant un transistor MOS de puissance incluant un transistor parasitique[1997/33]
Examination procedure13.06.2000Examination requested  [2000/32]
06.03.2006Despatch of a communication from the examining division (Time limit: M04)
17.07.2006Reply to a communication from the examining division
09.03.2007Communication of intention to grant the patent
03.07.2007Fee for grant paid
03.07.2007Fee for publishing/printing paid
Opposition(s)30.05.2008No opposition filed within time limit [2008/32]
Fees paidRenewal fee
07.01.1999Renewal fee patent year 03
29.02.2000Renewal fee patent year 04
28.02.2001Renewal fee patent year 05
28.02.2002Renewal fee patent year 06
28.02.2003Renewal fee patent year 07
27.02.2004Renewal fee patent year 08
28.02.2005Renewal fee patent year 09
27.02.2006Renewal fee patent year 10
28.02.2007Renewal fee patent year 11
Lapses during opposition  TooltipGB06.02.2008
[2009/30]
Documents cited:Search[A]US4893158  (MIHARA TERUYOSHI [JP], et al) [A] 1-8 * abstract *;
 [A]GB2281815  (INT RECTIFIER CORP [US]) [A] 3-8 * abstract *;
 [A]US4862233  (MATSUSHITA TSUTOMU [JP], et al) [A] 1,3,5,8 * abstract *;
 [A]EP0545488  (CONS RIC MICROELETTRONICA [IT], et al) [A] 1-8 * abstract *;
 [A]EP0512605  (PHILIPS NV [NL]) [A] 1-8 * abstract *;
 [A]DE4423733  (SIEMENS AG [DE]) [A] 1-8 * abstract *;
 [PA]EP0703620  (SGS THOMSON MICROELECTRONICS [IT], et al) [PA] 1-8