Extract from the Register of European Patents

About this file: EP0834816

EP0834816 - Microprocessor architecture capable of supporting multiple heterogenous processors [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  03.11.2000
Database last updated on 18.05.2019
Most recent event   Tooltip11.01.2008Lapse of the patent in a contracting state
New state(s): IT
published on 13.02.2008  [2008/07]
Applicant(s)For all designated states
Seiko Epson Corporation
4-1, Nishi-shinjuku 2-chome, Shinjuku-ku
Tokyo 163 / JP
[N/P]
Former [1998/15]For all designated states
SEIKO EPSON CORPORATION
4-1, Nishi-shinjuku 2-chome, Shinjuku-ku
Tokyo 163 / JP
Inventor(s)01 / Lentz, Derek J.
17400 Phillips Avenue
Los Gatos, California 95032 / US
02 / Hagiwara, Yasuaki
2250 Monroe Street, Apt. 274
Santa Clara, California 95050 / US
03 / Tang, Cheng-Long
1915 Ribisi Way
San Jose, California 95131 / US
04 / Lau, Te-Li
3075 Louis Road
Palo Alto, California 94303 / US
[1998/15]
Representative(s)Grünecker Patent- und Rechtsanwälte PartG mbB
Leopoldstraße 4
80802 München / DE
[N/P]
Former [1998/15]Grünecker, Kinkeldey, Stockmair & Schwanhäusser Anwaltssozietät
Maximilianstrasse 58
80538 München / DE
Application number, filing date97119364.407.07.1992
[1998/15]
Priority number, dateUS1991072689308.07.1991         Original published format: US 726893
[1998/15]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0834816
Date:08.04.1998
Language:EN
[1998/15]
Type: A3 Search report 
No.:EP0834816
Date:22.04.1998
[1998/17]
Type: B1 Patent specification 
No.:EP0834816
Date:05.01.2000
Language:EN
[2000/01]
Search report(s)(Supplementary) European search report - dispatched on:EP09.03.1998
ClassificationInternational:G06F15/16
[1998/15]
Designated contracting statesAT,   BE,   CH,   DE,   DK,   ES,   FR,   GB,   GR,   IT,   LI,   LU,   MC,   NL,   SE [1998/15]
TitleGerman:Mikroprozessorarchitektur mit der Möglichkeit zur Unterstützung mehrerer verschiedener Prozessoren[1998/15]
English:Microprocessor architecture capable of supporting multiple heterogenous processors[1998/15]
French:Architecture de microprocesseur pouvant prendre en charge plusieurs processeurs hétérogènes[1998/15]
Examination procedure05.11.1997Examination requested  [1998/15]
01.03.1999Despatch of communication of intention to grant (Approval: Yes)
07.07.1999Communication of intention to grant the patent
06.10.1999Fee for grant paid
06.10.1999Fee for publishing/printing paid
Parent application(s)   TooltipEP92914441.8  / EP0547246
Opposition(s)06.10.2000No opposition filed within time limit [2000/51]
Fees paidRenewal fee
05.11.1997Renewal fee patent year 03
05.11.1997Renewal fee patent year 04
05.11.1997Renewal fee patent year 05
05.11.1997Renewal fee patent year 06
29.07.1998Renewal fee patent year 07
29.07.1999Renewal fee patent year 08
Lapses during opposition  TooltipAT05.01.2000
BE05.01.2000
CH05.01.2000
ES05.01.2000
GR05.01.2000
IT05.01.2000
LI05.01.2000
NL05.01.2000
SE05.01.2000
DK05.04.2000
LU07.07.2000
MC31.07.2000
[2008/07]
Former [2007/29]AT05.01.2000
BE05.01.2000
CH05.01.2000
ES05.01.2000
GR05.01.2000
LI05.01.2000
NL05.01.2000
SE05.01.2000
DK05.04.2000
LU07.07.2000
MC31.07.2000
Former [2004/07]AT05.01.2000
BE05.01.2000
CH05.01.2000
ES05.01.2000
GR05.01.2000
LI05.01.2000
NL05.01.2000
SE05.01.2000
DK05.04.2000
MC31.07.2000
Former [2003/46]AT05.01.2000
BE05.01.2000
CH05.01.2000
ES05.01.2000
LI05.01.2000
NL05.01.2000
SE05.01.2000
DK05.04.2000
MC31.07.2000
Former [2003/09]AT05.01.2000
BE05.01.2000
CH05.01.2000
ES05.01.2000
LI05.01.2000
NL05.01.2000
SE05.01.2000
MC31.07.2000
Former [2002/42]AT05.01.2000
BE05.01.2000
CH05.01.2000
ES05.01.2000
LI05.01.2000
SE05.01.2000
MC31.07.2000
Former [2002/27]AT05.01.2000
BE05.01.2000
CH05.01.2000
ES05.01.2000
LI05.01.2000
SE05.01.2000
Former [2002/23]AT05.01.2000
BE05.01.2000
CH05.01.2000
LI05.01.2000
SE05.01.2000
Former [2001/08]AT05.01.2000
BE05.01.2000
CH05.01.2000
LI05.01.2000
Former [2000/52]CH05.01.2000
LI05.01.2000
Former [2000/50]CH10.04.2000
LI10.04.2000
Documents cited:Search[A]EP0324662  (EVANS & SUTHERLAND COMPUTER CO [US]) [A] 1-4 * page 2, line 41 - page 6, line 35; figure 1 *;
 [A]EP0222074  (IBM [US]) [A] 1,3 * column 5, line 38 - column 12, line 17; figures 1-2A,2C *
 [A]  BERNHARD QUATEMBER, "Protocol issues of the configurational management and the resolution of the contention problem in large-scale crossbar switch", PROCEEDING OF MELECON '83, ATHENS, GREECE, (19830524), pages 1 - 2, XP000014871 [A] 1-4 * the whole document *