Extract from the Register of European Patents

About this file: EP0862269

EP0862269 - Data latch circuit device with flip-flop of semi-conductor memory of synchronous DRAM [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  12.09.2003
Database last updated on 14.11.2018
Most recent event   Tooltip12.09.2003No opposition filed within time limitpublished on 29.10.2003  [2003/44]
Applicant(s)For all designated states
NEC Corporation
7-1, Shiba 5-chome Minato-ku
Tokyo 108-8001 / JP
For all designated states
NEC Electronics Corporation
1753 Shimonumabe Nakahara-ku
Kawasaki, Kanagawa 211-8668 / JP
[N/P]
Former [2003/15]For all designated states
NEC CORPORATION
7-1, Shiba 5-chome, Minato-ku
Tokyo / JP
For all designated states
NEC Electronics Corporation
1753 Shimonumabe, Nakahara-ku
Kawasaki, Kanagawa 211-8668 / JP
Former [2002/45]For all designated states
NEC CORPORATION
7-1, Shiba 5-chome, Minato-ku
Tokyo / JP
Former [1998/36]For all designated states
NEC CORPORATION
7-1, Shiba 5-chome Minato-ku
Tokyo / JP
Inventor(s)01 / Fukuda, Takeshi, NEC IC Microcomputer Syst. Ltd.
403-53 Kosugimachi 1-chome, Nakahara-ku
Kawasaki-shi, Kanagawa / JP
[1998/36]
Representative(s)Glawe, Delfs, Moll
Partnerschaft mbB von
Patent- und Rechtsanwälten
Postfach 26 01 62
80058 München / DE
[N/P]
Former [1998/36]Glawe, Delfs, Moll & Partner
Patentanwälte Postfach 26 01 62
80058 München / DE
Application number, filing date98103393.926.02.1998
[1998/36]
Priority number, dateJP1997004412627.02.1997         Original published format: JP 4412697
[1998/36]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0862269
Date:02.09.1998
Language:EN
[1998/36]
Type: A3 Search report 
No.:EP0862269
Date:22.11.2000
[2000/47]
Type: B1 Patent specification 
No.:EP0862269
Date:06.11.2002
Language:EN
[2002/45]
Search report(s)(Supplementary) European search report - dispatched on:EP06.10.2000
ClassificationInternational:H03K3/037
[1998/36]
Designated contracting statesDE,   FR,   GB [2001/32]
Former [1998/36]AT,  BE,  CH,  DE,  DK,  ES,  FI,  FR,  GB,  GR,  IE,  IT,  LI,  LU,  MC,  NL,  PT,  SE 
TitleGerman:Datenverriegelungs-Schaltungsvorrichtung mit synchronem Halbleiterflipflop-DRAM-Speicher[1998/36]
English:Data latch circuit device with flip-flop of semi-conductor memory of synchronous DRAM[1998/36]
French:Dispositif de circuit à verrouillage de données avec bascule de mémoire semi-conductrice DRM synchrone[1998/36]
Examination procedure11.10.2000Examination requested  [2000/49]
30.01.2002Despatch of communication of intention to grant (Approval: Yes)
08.05.2002Communication of intention to grant the patent
05.08.2002Fee for grant paid
05.08.2002Fee for publishing/printing paid
Opposition(s)07.08.2003No opposition filed within time limit [2003/44]
Fees paidRenewal fee
21.02.2000Renewal fee patent year 03
15.02.2001Renewal fee patent year 04
15.02.2002Renewal fee patent year 05
Documents cited:Search[A]US5559458  (HOLLER JR PAUL T [US]) [A] 1,4 * the whole document *;
 [A]EP0283202  (AMERICAN TELEPHONE & TELEGRAPH [US]) [A] 1,4 * the whole document *;
 [DA]JPH05327422  ;
 [A]US5369377  (BENHAMIDA BOUBEKEUR [US]) [A] 1,4 * abstract *;
 [A]US4982116  (LEE MINRU [US]) [A] 1,4 * abstract *
 [DA]  - PATENT ABSTRACTS OF JAPAN, (19940311), vol. 018, no. 148, Database accession no. (E - 1522), [DA] 1,4 * abstract *