Extract from the Register of European Patents

About this file: EP0862062

EP0862062 - Circuit board inspection apparatus and method [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  19.09.2003
Database last updated on 22.03.2019
Most recent event   Tooltip17.02.2006Lapse of the patent in a contracting statepublished on 05.04.2006  [2006/14]
Applicant(s)For all designated states
Nidec-Read Corporation
126, Megawa, Makishima-cho Uji-city
Kyoto 611-0041 / JP
[N/P]
Former [1998/36]For all designated states
Nidec-Read Corporation
126, Megawa, Makishima-cho
Uji-city, Kyoto 611-0041 / JP
Inventor(s)01 / Takahashi, Tadashi
126, Megawa, Makishima-cho
Uji-City, Kyoto 611-0041 / JP
[1998/36]
Representative(s)von Fischern, Bernhard , et al
Hoffmann - Eitle
Patent- und Rechtsanwälte
Arabellastrasse 4
81925 München / DE
[N/P]
Former [1998/36]von Fischern, Bernhard, Dipl.-Ing. , et al
Hoffmann - Eitle, Patent- und Rechtsanwälte, Arabellastrasse 4
81925 München / DE
Application number, filing date98103455.627.02.1998
[1998/36]
Priority number, dateJP1997004611428.02.1997         Original published format: JP 4611497
[1998/36]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0862062
Date:02.09.1998
Language:EN
[1998/36]
Type: A3 Search report 
No.:EP0862062
Date:02.02.2000
[2000/05]
Type: B1 Patent specification 
No.:EP0862062
Date:13.11.2002
Language:EN
[2002/46]
Search report(s)(Supplementary) European search report - dispatched on:EP17.12.1999
ClassificationInternational:G01R31/312, G01R31/28
[1998/36]
Designated contracting statesDE,   FR,   GB [2000/41]
Former [1998/36]AT,  BE,  CH,  DE,  DK,  ES,  FI,  FR,  GB,  GR,  IE,  IT,  LI,  LU,  MC,  NL,  PT,  SE 
TitleGerman:Verfahren und Vorrichtung zum Prüfen von Leiterplatten[1998/36]
English:Circuit board inspection apparatus and method[1998/36]
French:Procédé et dispositif de contrôle de cartes de circuit[1998/36]
Examination procedure17.07.2000Examination requested  [2000/37]
03.08.2000Loss of particular rights, legal effect: designated state(s)
15.11.2000Despatch of communication of loss of particular rights: designated state(s) AT, BE, CH, DK, ES, FI, GR, IE, IT, LI, LU, MC, NL, PT, SE
21.06.2001Request for accelerated examination filed
06.09.2001Despatch of a communication from the examining division (Time limit: M04)
06.09.2001Decision about request for accelerated examination - accepted: Yes
14.01.2002Reply to a communication from the examining division
25.03.2002Despatch of communication of intention to grant (Approval: Yes)
31.05.2002Communication of intention to grant the patent
29.08.2002Fee for grant paid
29.08.2002Fee for publishing/printing paid
Opposition(s)14.08.2003No opposition filed within time limit [2003/45]
Fees paidRenewal fee
16.02.2000Renewal fee patent year 03
16.02.2001Renewal fee patent year 04
26.02.2002Renewal fee patent year 05
Penalty fee
Penalty fee Rule 85a EPC 1973
01.09.2000AT   M01   Not yet paid
01.09.2000BE   M01   Not yet paid
01.09.2000CH   M01   Not yet paid
01.09.2000DK   M01   Not yet paid
01.09.2000ES   M01   Not yet paid
01.09.2000FI   M01   Not yet paid
01.09.2000GR   M01   Not yet paid
01.09.2000IE   M01   Not yet paid
01.09.2000IT   M01   Not yet paid
01.09.2000LU   M01   Not yet paid
01.09.2000MC   M01   Not yet paid
01.09.2000NL   M01   Not yet paid
01.09.2000PT   M01   Not yet paid
01.09.2000SE   M01   Not yet paid
Lapses during opposition  TooltipFR13.11.2002
[2006/14]
Documents cited:Search[X]EP0636887  (GENRAD INC [US]) [X] 1-14 * abstract * * column 1, line 3 - line 10 * * column 5, line 8 - line 52 *;
 [X]GB2143954  (SHARETREE LTD) [X] 1-14 * abstract *;
 [X]JPH0854448  (OKANO HIGHTECH KK) [X] 1-14 * figures 2,3 *;
 [L]US5747999  (YAMAOKA SYUUZI [JP]) [L] * abstract * * column 2, line 14 - line 60 * * column 4, line 13 - line 59 *;
 [X]US5498964  (KERSCHNER RONALD K [US], et al) [X] 1,14 * abstract *;
 [X]EP0633478  (SPEA SRL [IT]) [X] 1,14 * abstract *