Extract from the Register of European Patents

About this file: EP0905904

EP0905904 - Semiconductor integrated circuit having tri-state logic gate circuit [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  03.09.2004
Database last updated on 27.01.2020
Most recent event   Tooltip03.09.2004No opposition filed within time limitpublished on 20.10.2004  [2004/43]
Applicant(s)For all designated states
Oki Electric Industry Co., Ltd.
7-12, Toranomon 1-chome Minato-ku
Tokyo / JP
[N/P]
Former [1999/13]For all designated states
Oki Electric Industry Co., Ltd.
7-12, Toranomon 1-chome Minato-ku
Tokyo / JP
Inventor(s)01 / Kawagoe, Masakuni
c/o Oki Micro Design Miyazaki Co., Ltd.
9-2, Yamato-cho, Miyazaki-shi, Miyazaki / JP
[1999/13]
Representative(s)Betten & Resch
Patent- und Rechtsanwälte PartGmbB
Postfach 10 02 51
80076 München / DE
[N/P]
Former [1999/13]Betten & Resch
Reichenbachstrasse 19
80469 München / DE
Application number, filing date98116237.327.08.1998
[1999/13]
Priority number, dateJP1997025953225.09.1997         Original published format: JP 25953297
[1999/13]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0905904
Date:31.03.1999
Language:EN
[1999/13]
Type: A3 Search report 
No.:EP0905904
Date:26.01.2000
[2000/04]
Type: B1 Patent specification 
No.:EP0905904
Date:29.10.2003
Language:EN
[2003/44]
Search report(s)(Supplementary) European search report - dispatched on:EP09.12.1999
ClassificationInternational:H03K19/094, H03K19/003, H03K19/0185, G11C5/14
[2000/04]
Former International [1999/13]H03K19/094
Designated contracting statesDE,   FR,   NL [2000/40]
Former [1999/13]AT,  BE,  CH,  CY,  DE,  DK,  ES,  FI,  FR,  GB,  GR,  IE,  IT,  LI,  LU,  MC,  NL,  PT,  SE 
TitleGerman:Integrierte Halbleiterschaltung mit logischem Gatter mit drei Betriebszuständen[1999/13]
English:Semiconductor integrated circuit having tri-state logic gate circuit[1999/13]
French:Circuit intégré semi-conducteur avec portes logiques à trois états[1999/13]
Examination procedure05.05.2000Examination requested  [2000/26]
07.02.2003Communication of intention to grant the patent
04.06.2003Fee for grant paid
04.06.2003Fee for publishing/printing paid
Opposition(s)30.07.2004No opposition filed within time limit [2004/43]
Fees paidRenewal fee
31.08.2000Renewal fee patent year 03
31.08.2001Renewal fee patent year 04
02.09.2002Renewal fee patent year 05
29.08.2003Renewal fee patent year 06
Documents cited:Search[A]US5631867  (AKAMATSU HIROSHI ET AL) [A] 1-3,8 * column 3, line 1 - column 4, line 11; figures 11,12 *;
 [A]JPS62165426  ;
 [A]US4617482  (MATSUDA KOHEI) [A] 1,8 * figure 1 *;
 [A]US5124578  (WORLEY EUGENE R ET AL) [A] 1,8 * the whole document *
 [A]  - PATENT ABSTRACTS OF JAPAN, (19880107), vol. 012, no. 003, Database accession no. (E - 570), & JP62165426 A 19870722 (HITACHI MICRO COMPUT ENG LTD;OTHERS: 01) [A] 1,8 * abstract *