Extract from the Register of European Patents

About this file: EP0933807

EP0933807 - Method for manufacturing a power semiconductor device [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  20.04.2007
Database last updated on 19.03.2019
Most recent event   Tooltip21.11.2008Change - lapse in a contracting state
Updated state(s): FR
published on 24.12.2008  [2008/52]
Applicant(s)For all designated states
Infineon Technologies AG
St.-Martin-Strasse 53
81669 München / DE
[2006/24]
Former [2002/01]For all designated states
Infineon Technologies AG
St.-Martin-Strasse 53
81669 München / DE
Former [1999/31]For all designated states
SIEMENS AKTIENGESELLSCHAFT
Wittelsbacherplatz 2
80333 München / DE
Inventor(s)01 / Reznik, Daniel, Dr.
Heinrich-Heine-Strasse 6a
80686 München / DE
02 / Schulze, Hans-Joachim, Dr.
Ottostrasse 60f
85521 Ottobrunn / DE
03 / Wolfgang, Eckhard
Murnauer Strasse 237
31379 München / DE
[1999/31]
Representative(s)Westphal, Mussgnug & Partner Patentanwälte mbB
Werinherstrasse 79
81541 München / DE
[N/P]
Former [2002/01]Patentanwälte Westphal, Mussgnug & Partner
Mozartstrasse 8
80336 München / DE
Application number, filing date98124404.921.12.1998
[1999/31]
Priority number, dateDE199810419203.02.1998         Original published format: DE 19804192
[1999/31]
Filing languageDE
Procedural languageDE
PublicationType: A2 Application without search report 
No.:EP0933807
Date:04.08.1999
Language:DE
[1999/31]
Type: A3 Search report 
No.:EP0933807
Date:26.01.2000
[2000/04]
Type: B1 Patent specification 
No.:EP0933807
Date:14.06.2006
Language:DE
[2006/24]
Search report(s)(Supplementary) European search report - dispatched on:EP10.12.1999
ClassificationInternational:H01L21/331, H01L21/332
[1999/31]
Designated contracting statesCH,   DE,   FR,   GB,   IT,   LI,   SE [2000/40]
Former [1999/31]AT,  BE,  CH,  CY,  DE,  DK,  ES,  FI,  FR,  GB,  GR,  IE,  IT,  LI,  LU,  MC,  NL,  PT,  SE 
TitleGerman:Verfahren zur Herstellung eines Leistungshalbleiterbauelementes[1999/31]
English:Method for manufacturing a power semiconductor device[1999/31]
French:Procédé de fabrication d'un dispositif semi-conducteur de puissance[1999/31]
Examination procedure26.07.2000Examination requested  [2000/38]
21.12.2005Communication of intention to grant the patent
23.03.2006Fee for grant paid
23.03.2006Fee for publishing/printing paid
Opposition(s)15.03.2007No opposition filed within time limit [2007/21]
Fees paidRenewal fee
18.12.2000Renewal fee patent year 03
18.12.2001Renewal fee patent year 04
17.12.2002Renewal fee patent year 05
16.12.2003Renewal fee patent year 06
17.12.2004Renewal fee patent year 07
21.12.2005Renewal fee patent year 08
Lapses during opposition  TooltipFR14.06.2006
GB14.06.2006
IT14.06.2006
SE14.09.2006
CH31.12.2006
LI31.12.2006
[2008/52]
Former [2008/22]GB14.06.2006
IT14.06.2006
SE14.09.2006
CH31.12.2006
LI31.12.2006
FR09.03.2007
Former [2008/12]GB14.06.2006
IT14.06.2006
SE14.09.2006
CH31.12.2006
LI31.12.2006
Former [2007/29]GB14.06.2006
SE14.09.2006
Former [2006/49]SE14.09.2006
Documents cited:Search[XY]JPH01145860  ;
 [DY]US5608237  (AIZAWA YOSHIAKI [JP], et al) [DY] 4 * column W *;
 [XY]  - PATENT ABSTRACTS OF JAPAN, (19890907), vol. 13, no. 404, Database accession no. (E - 817), [X] 1-3 * abstract * [Y] 4,5
 [DY]  - T. OGURA ET LA., "High frequency 6000 V double gate GTOs with buried gate structure", PROCEEDINGS OF 1990 INTERNATIONAL SYMPOSIUM ON POWER SWMICONDUCTOR DEVICES & ICS, tokyo, japan, (1990), pages 252 - 255, XP002123881 [DY] 5 * the whole document *