Extract from the Register of European Patents

About this file: EP0877419

EP0877419 - Methods of electroplating solder bumps of uniform height on integrated circuit substrates [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  10.10.2008
Database last updated on 25.01.2020
Most recent event   Tooltip03.06.2011Lapse of the patent in a contracting state
New state(s): IT
published on 06.07.2011  [2011/27]
Applicant(s)For all designated states
Unitive International Limited
Caracasbaaiweg 201
Curacao / AN
[2001/37]
Former [1998/46]For all designated states
MCNC
3021 Cornwallis Road, Post Office Box 12889
Research Triangle Park, North Carolina 27709 / US
Inventor(s)01 / Rinne, Glenn A.
206 Excalibur Court
Cary, North Carolina 27513 / US
02 / Lizzul, Christine
206 Excalibur Court
Cary, North Carolina 27513 / US
[1998/46]
Representative(s)Moreland, David , et al
Marks & Clerk LLP
Aurora
120 Bothwell Street
Glasgow G2 7JS / GB
[N/P]
Former [2005/16]Moreland, David, Dr. , et al
Marks & Clerk Scotland 19 Royal Exchange Square
Glasgow G1 3AE / GB
Former [2001/37]MacDougall, Donald Carmichael , et al
Cruikshank & Fairweather 19 Royal Exchange Square
Glasgow G1 3AE, Scotland / GB
Former [1998/46]MacDougall, Donald Carmichael
Cruikshank & Fairweather 19 Royal Exchange Square
Glasgow G1 3AE, Scotland / GB
Application number, filing date98303275.628.04.1998
[1998/46]
Priority number, dateUS1997085407509.05.1997         Original published format: US 854075
[1998/46]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0877419
Date:11.11.1998
Language:EN
[1998/46]
Type: A3 Search report 
No.:EP0877419
Date:18.08.1999
[1999/33]
Type: B1 Patent specification 
No.:EP0877419
Date:05.12.2007
Language:EN
[2007/49]
Search report(s)(Supplementary) European search report - dispatched on:EP01.07.1999
ClassificationInternational:H01L21/60
[1998/46]
Designated contracting statesAT,   BE,   CH,   DE,   DK,   ES,   FI,   FR,   GB,   IE,   IT,   LI,   NL,   SE [2000/21]
Former [2000/17]AT,  BE,  CH,  DE,  DK,  ES,  FI,  FR,  GB,  IE,  IT,  LI,  NL 
Former [1998/46]AT,  BE,  CH,  CY,  DE,  DK,  ES,  FI,  FR,  GB,  GR,  IE,  IT,  LI,  LU,  MC,  NL,  PT,  SE 
TitleGerman:Elektrochemisches Abscheiden von Lötbällen mit einheitlicher Höhe auf Halbleitersubstraten[1998/46]
English:Methods of electroplating solder bumps of uniform height on integrated circuit substrates[1998/46]
French:Méthode de dépôt électrolytique de bosses de soudure uniforme en hauteur sur un substrat semiconducteur[1998/46]
Examination procedure04.02.2000Examination requested  [2000/14]
13.10.2004Despatch of a communication from the examining division (Time limit: M06)
03.03.2005Reply to a communication from the examining division
03.11.2006Despatch of a communication from the examining division (Time limit: M06)
16.04.2007Reply to a communication from the examining division
18.06.2007Communication of intention to grant the patent
19.10.2007Fee for grant paid
19.10.2007Fee for publishing/printing paid
Divisional application(s)EP07020495.3  / EP1892754
Opposition(s)08.09.2008No opposition filed within time limit [2008/46]
Fees paidRenewal fee
27.04.2000Renewal fee patent year 03
25.04.2001Renewal fee patent year 04
26.04.2002Renewal fee patent year 05
24.04.2003Renewal fee patent year 06
28.04.2004Renewal fee patent year 07
20.04.2005Renewal fee patent year 08
26.04.2006Renewal fee patent year 09
27.04.2007Renewal fee patent year 10
Penalty fee
Penalty fee Rule 85a EPC 1973
21.03.2000SE   M01   Fee paid on   29.03.2000
Lapses during opposition  TooltipAT05.12.2007
BE05.12.2007
CH05.12.2007
DK05.12.2007
FI05.12.2007
LI05.12.2007
NL05.12.2007
SE05.03.2008
DE06.03.2008
ES16.03.2008
GB28.04.2008
IE28.04.2008
IT30.04.2008
[2011/27]
Former [2009/30]AT05.12.2007
BE05.12.2007
CH05.12.2007
DK05.12.2007
FI05.12.2007
LI05.12.2007
NL05.12.2007
SE05.03.2008
DE06.03.2008
ES16.03.2008
GB28.04.2008
IE28.04.2008
Former [2008/48]AT05.12.2007
BE05.12.2007
CH05.12.2007
DK05.12.2007
FI05.12.2007
LI05.12.2007
NL05.12.2007
SE05.03.2008
DE06.03.2008
ES16.03.2008
Former [2008/46]AT05.12.2007
BE05.12.2007
CH05.12.2007
DK05.12.2007
FI05.12.2007
LI05.12.2007
NL05.12.2007
SE05.03.2008
ES16.03.2008
Former [2008/40]AT05.12.2007
BE05.12.2007
CH05.12.2007
FI05.12.2007
LI05.12.2007
NL05.12.2007
SE05.03.2008
ES16.03.2008
Former [2008/29]AT05.12.2007
CH05.12.2007
FI05.12.2007
LI05.12.2007
NL05.12.2007
SE05.03.2008
ES16.03.2008
Former [2008/24]CH05.12.2007
FI05.12.2007
LI05.12.2007
NL05.12.2007
SE05.03.2008
ES16.03.2008
Former [2008/23]CH05.12.2007
LI05.12.2007
NL05.12.2007
SE05.03.2008
ES16.03.2008
Documents cited:Search[A]JPS5773953  ;
 [A]US4142202  (CSILLAG ANDREAS ET AL) [A] 1-27 * the whole document *;
 [DA]JPH05166815  ;
 [A]  - PATENT ABSTRACTS OF JAPAN, (19820811), vol. 006, no. 151, Database accession no. (E - 124), & JP57073953 A 19820508 (NEC HOME ELECTRONICS LTD) [A] 1,8,22 * abstract *
 [DA]  - PATENT ABSTRACTS OF JAPAN, (19931014), vol. 017, no. 568, Database accession no. (E - 1447), & JP05166815 A 19930702 (MATSUSHITA ELECTRON CORP) [DA] 1-27 * abstract *
 [A]  - DELMONTE L A, "Fabrication of gold bumps for integrated circuit terminal contact", 23RD ELECTRONIC COMPONENTS CONFERENCE, WASHINGTON, DC, USA, 14-16 MAY 1973, 1973, New York, NY, USA, IEEE, USA, pages 21 - 25, XP002106381 [A] 1-27 * page 21, column 2, paragraph 4 - page 22, column 1, paragraph 4 *