Extract from the Register of European Patents

About this file: EP0889416

EP0889416 - Digital signal processor architecture optimized for performing fast fourier transforms [Right-click to bookmark this link]
StatusThe application has been refused
Status updated on  14.08.2009
Database last updated on 19.07.2018
Most recent event   Tooltip14.08.2009Refusal of applicationpublished on 16.09.2009  [2009/38]
Applicant(s)For all designated states
LUCENT TECHNOLOGIES INC.
600 Mountain Avenue
Murray Hill, NJ 07974-0636 / US
[N/P]
Former [2009/36]For all designated states
LUCENT TECHNOLOGIES INC.
600 Mountain Avenue
Murray Hill NJ 07974-0636 / US
Former [1999/01]For all designated states
LUCENT TECHNOLOGIES INC.
600 Mountain Avenue
Murray Hill, New Jersey 07974-0636 / US
Inventor(s)01 / Prasad, Mohit K.
5630 Halbea Street
Bethlehem, Pennsylvania 18017 / US
02 / Srinivas, Hosahalli R.
554 Benner Road, Apartment No. 102
Allentown, Pennsylvania 18104 / US
[1999/01]
Representative(s)Williams, David John , et al
Page White & Farrer
Bedford House
John Street
London
WC1N 2BF / GB
[N/P]
Former [2001/20]Williams, David John , et al
Page White & Farrer, 54 Doughty Street
London WC1N 2LS / GB
Former [1999/01]Watts, Christopher Malcolm Kelway, Dr.
Lucent Technologies (UK) Ltd, 5 Mornington Road
Woodford Green Essex, IG8 0TU / GB
Application number, filing date98304936.223.06.1998
[1999/01]
Priority number, dateUS1997088469130.06.1997         Original published format: US 884691
[1999/01]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0889416
Date:07.01.1999
Language:EN
[1999/01]
Type: A3 Search report 
No.:EP0889416
Date:09.02.2000
[2000/06]
Search report(s)(Supplementary) European search report - dispatched on:EP23.12.1999
ClassificationInternational:G06F17/14
[1999/01]
Designated contracting statesDE,   FR,   GB [2000/42]
Former [1999/01]AT,  BE,  CH,  CY,  DE,  DK,  ES,  FI,  FR,  GB,  GR,  IE,  IT,  LI,  LU,  MC,  NL,  PT,  SE 
TitleGerman:Digitaler Signalprozessor optimiert für die Ausführung schneller Fourier-Transformationen[1999/01]
English:Digital signal processor architecture optimized for performing fast fourier transforms[1999/01]
French:Processeur de signal numérique optimisé pour l'éxecution des transformations rapides de Fourier[1999/01]
Examination procedure27.07.2000Examination requested  [2000/38]
27.12.2006Despatch of a communication from the examining division (Time limit: M04)
03.05.2007Reply to a communication from the examining division
26.06.2008Date of oral proceedings
04.07.2008Despatch of communication that the application is refused, reason: substantive examination [2009/38]
04.07.2008Minutes of oral proceedings despatched
09.08.2009Application refused, date of legal effect [2009/38]
Appeal following examination05.09.2008Appeal received No.  T2361/08
24.07.2009Result of appeal procedure: appeal of the applicant inadmissible
Fees paidRenewal fee
16.06.2000Renewal fee patent year 03
26.03.2001Renewal fee patent year 04
23.05.2002Renewal fee patent year 05
23.06.2003Renewal fee patent year 06
11.06.2004Renewal fee patent year 07
13.06.2005Renewal fee patent year 08
12.06.2006Renewal fee patent year 09
14.06.2007Renewal fee patent year 10
12.06.2008Renewal fee patent year 11
Penalty fee
Additional fee for renewal fee
30.06.200912   M06   Not yet paid
Documents cited:Search[Y]EP0660245  (MOTOROLA INC [US]) [Y] 9-14 * page 2, line 8 - line 46 * * page 3, line 38 - page 4, line 49; figure 2 *;
 [XY]  PRASAD ET AL, "Half-rate GSM vocoder implementation on a dual mac digital signal processor", 1997 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING, (19970421), vol. 1, pages 619 - 622, XP000789223 [X] 1-8 * the whole document * [Y] 9-14
 [A]  WEISS, "DSP chip set does 24-bit, 1024-point FFT in 129 µsec", EDN - ELECTRICAL DESIGN NEWS, Newton, MA, US, (19930902), no. 18, page 144&146, XP000395148 [A] * page 144, column M, line 1 - page 146, column R, line L *