-
EP1019959
European procedure
Extract from the Register of European Patents
EP About this file: EP1019959
| EP1019959 - INTERCONNECT STRUCTURE WITH A LOW PERMITTIVITY DIELECTRIC LAYER [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 19.12.2003 Database last updated on 23.04.2024 | Most recent event Tooltip | 17.02.2006 | Lapse of the patent in a contracting state New state(s): FR | published on 05.04.2006 [2006/14] | Applicant(s) | For all designated states ADVANCED MICRO DEVICES, INC. One AMD Place Mail Stop 68 P.O. Box 3453 Sunnyvale CA 94088-3453 / US | [N/P] |
| Former [2003/07] | For all designated states ADVANCED MICRO DEVICES INC. One AMD Place, Mail Stop 68 Sunnyvale, California 94088-3453 / US | ||
| Former [2000/29] | For all designated states ADVANCED MICRO DEVICES INC. One AMD Place, Mail Stop 68 Sunnyvale, California 94088-3453 / US | Inventor(s) | 01 /
MAY, Charles 4296 SE Augusta Loop Gresham OR 97080 / US | 02 /
CHEUNG, Robin 21428 Krzich Pl Cupertino, CA 95014 / US | [2000/38] |
| Former [2000/29] | 01 /
MAY, Charles 10503 Ames Lane Austin, TX 78739 / US | ||
| 02 /
CHEUNG, Robin 19889 Baywood Drive Cupertino, CA 95014 / US | Representative(s) | Sanders, Peter Colin Christopher, et al Brookes Batchellor 1 Boyne Park Tunbridge Wells Kent TN4 8EL / GB | [N/P] |
| Former [2000/29] | Sanders, Peter Colin Christopher, et al BROOKES & MARTIN High Holborn House 52/54 High Holborn London WC1V 6SE / GB | Application number, filing date | 98913232.9 | 27.03.1998 | [2000/29] | WO1998US06139 | Priority number, date | US19970939066 | 29.09.1997 Original published format: US 939066 | [2000/29] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | WO9917359 | Date: | 08.04.1999 | Language: | EN | [1999/14] | Type: | A1 Application with search report | No.: | EP1019959 | Date: | 19.07.2000 | Language: | EN | The application published by WIPO in one of the EPO official languages on 08.04.1999 takes the place of the publication of the European patent application. | [2000/29] | Type: | B1 Patent specification | No.: | EP1019959 | Date: | 12.02.2003 | Language: | EN | [2003/07] | Search report(s) | International search report - published on: | EP | 08.04.1999 | Classification | IPC: | H01L21/768, H01L21/3105 | [2000/29] | CPC: |
H01L21/02126 (US);
H01L21/02134 (US);
H01L21/31053 (EP,US);
H01L21/76819 (EP,US);
H01L23/5329 (EP,US);
H01L21/3121 (US);
| C-Set: |
H01L2924/0002, H01L2924/00 (EP,US)
| Designated contracting states | DE, FR, GB, NL [2000/29] | Title | German: | LEITERBAHNSTRUKTUR MIT EINEM DIELEKTRIKUM MIT EINER NIEDRIGEN PERMITIVITÄT | [2000/29] | English: | INTERCONNECT STRUCTURE WITH A LOW PERMITTIVITY DIELECTRIC LAYER | [2000/29] | French: | STRUCTURE D'INTERCONNEXION DOTEE D'UNE COUCHE DIELECTRIQUE A FAIBLE PERMITTIVITE | [2000/29] | Entry into regional phase | 17.02.2000 | National basic fee paid | 17.02.2000 | Designation fee(s) paid | 17.02.2000 | Examination fee paid | Examination procedure | 12.02.1999 | Request for preliminary examination filed International Preliminary Examining Authority: EP | 17.02.2000 | Examination requested [2000/29] | 29.06.2001 | Despatch of a communication from the examining division (Time limit: M04) | 05.07.2001 | Reply to a communication from the examining division | 13.03.2002 | Despatch of a communication from the examining division (Time limit: M04) | 10.05.2002 | Reply to a communication from the examining division | 23.07.2002 | Communication of intention to grant the patent | 25.11.2002 | Fee for grant paid | 25.11.2002 | Fee for publishing/printing paid | Opposition(s) | 13.11.2003 | No opposition filed within time limit [2004/06] | Fees paid | Renewal fee | 17.02.2000 | Renewal fee patent year 03 | 05.03.2001 | Renewal fee patent year 04 | 04.03.2002 | Renewal fee patent year 05 |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | FR | 12.02.2003 | NL | 12.02.2003 | [2006/14] |
| Former [2003/41] | NL | 12.02.2003 | Cited in | International search | [X]US5498574 (SASAKI SHUUZOU [JP]) [X] 1,10-12,20,21,24 * column 2, line 25 - column 2, line 30 *; | [X]US5212114 (GREWAL VIRINDER-SINGH [DE], et al) [X] 1,20,24 * column 1, line 56 - column 2, line 31 *; | [X]US5478436 (WINEBARGER PAUL M [US], et al) [X] 1,20,24 * figure 2 *; | [A] - IDA J ET AL, "Reduction of wiring capacitance with new low dielectric SiOF interlayer film for high speed/low power sub-half micron CMOS", 1994 SYMPOSIUM ON VLSI TECHNOLOGY. DIGEST OF TECHNICAL PAPERS (CAT. NO.94CH3433-0), PROCEEDINGS OF 1994 VLSI TECHNOLOGY SYMPOSIUM, HONOLULU, HI, USA, 7-9 JUNE 1994, ISBN 0-7803-1921-4, 1994, NEW YORK, NY, USA, IEEE, USA, pages 59 - 60, XP000498582 [A] * the whole document * | [A] - JENG S -P ET AL, "Highly porous interlayer dielectric for interconnect capacitance reduction", 1995 SYMPOSIUM ON VLSI TECHNOLOGY. DIGEST OF TECHNICAL PAPERS (IEEE CAT. NO.95CH35781), 1995 SYMPOSIUM ON VLSI TECHNOLOGY. DIGEST OF TECHNICAL PAPERS, KYOTO, JAPAN, 6-8 JUNE 1995, ISBN 0-7803-2602-4, 1995, TOKYO, JAPAN, JAPAN SOC. APPL. PHYS, JAPAN, pages 61 - 62, XP000580830 [A] * the whole document * | [A] - JAIN M K ET AL, "A novel high performance integration scheme using fluorinated-SiO/sub 2/ and hydrogen silsesquioxane for capacitance reduction", INSPEC, INSTITUTE OF ELECTRICAL ENGINEERS, STEVENAGE, GB, XP002069622 [A] * abstract * | [ ] - 1996 PROCEEDINGS THIRTEENTH INTERNATIONAL VLSI MULTILEVEL INTERCONNECTION CONFERENCE (VMIC), PROCEEDINGS OF THIRTEENTH INTERNATIONAL VLSI MULTILEVEL INTERCONNECTION (V-MIC) CONFERENCE, SANTA CLARA, CA, USA, 18-20 JUNE 1996, 1996, TAMPA, FL, USA, VMIC, USA, pages 23 - 27, XP002068951 | Examination | JPH0758203 |