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Extract from the Register of European Patents

Citations: EP0974112

Cited inInternational search
Type:Non-patent literature
Publication information:[X]  - GHOSH I ET AL, "DESIGN FOR HIERARCHICAL TESTABILITY OF RTL CIRCUITS OBTAINED BY BEHAVIORAL SYNTHESIS", INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, AUSTIN, OCT. 2 - 4, 1995, INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, (19951002), pages 173 - 179, XP000631910 [X] 1,2 * abstract *
Type:Non-patent literature
Publication information:[A]  - VUAY NAGASAMY ET AL, "SPECIFICATION, PLANNING, AND SYNTHESIS", IEEE DESIGN & TEST OF COMPUTERS, (19920601), vol. 9, no. 2, pages 58 - 68, XP000306630 [A] 1-5 * page 60, column R, lines 20-37 * * page 62, column M, line 17 - column R, line 25; figure 2 *
DOI: http://dx.doi.org/10.1109/54.143146
Type:Non-patent literature
Publication information:[A]  - GAJSKI D D ET AL, "INTRODUCTION TO HIGH-LEVEL SYNTHESIS", IEEE DESIGN & TEST OF COMPUTERS, (19941221), vol. 11, no. 4, pages 44 - 54, XP000498505 [A] 1-7 * page 48, column R, line 16 - page 50, column M, line 15 *
DOI: http://dx.doi.org/10.1109/54.329454
Type:Non-patent literature
Publication information:[A]  - MAN DE H ET AL, "ARCHITECTURE-DRIVEN SYNTHESIS TECHNIQUES FOR VLSI INPLEMENTATION OFDSP ALGORITHMS", PROCEEDINGS OF THE IEEE, (19900201), vol. 78, no. 2, pages 319 - 335, XP000128907 [A] 1-21 * page 322, column R, lines 36-51; figure 2 *
DOI: http://dx.doi.org/10.1109/5.52215
Cited inExamination
Type:Patent literature
Publication No.:US5493508