Extract from the Register of European Patents

About this file: EP0974112

EP0974112 - METHOD FOR DESIGNING COMPLEX, DIGITAL AND INTEGRATED CIRCUITS AND A CIRCUIT STRUCTURE FOR CARRYING OUT SAID METHOD [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  23.03.2007
Database last updated on 19.07.2019
Most recent event   Tooltip23.03.2007Application deemed to be withdrawnpublished on 25.04.2007  [2007/17]
Applicant(s)For all designated states
Böthel, Andreas Frank
Feuerbachstr. 12
4105 Leipzig / DE
[2000/04]
Inventor(s)01 / see applicant
...
[2000/04]
Representative(s)Röther, Peter
Patentanwälte Dr. Brundert & Röther Kolkmannskamp 6
44879 Bochum / DE
[N/P]
Former [2000/04]Röther, Peter, Dipl.-Phys.
Patentanwalt Vor dem Tore 16a
47279 Duisburg / DE
Application number, filing date98930641.008.04.1998
[2000/04]
WO1998DE01019
Priority number, dateDE199711475610.04.1997         Original published format: DE 19714756
DE199713104319.07.1997         Original published format: DE 19731043
[2000/04]
Filing languageDE
Procedural languageDE
PublicationType: A1  Application with search report
No.:WO9845794
Date:15.10.1998
Language:DE
[1998/41]
Type: A1 Application with search report 
No.:EP0974112
Date:26.01.2000
Language:DE
The application has been published by WIPO in one of the EPO official languages on 15.10.1998
[2000/04]
Search report(s)International search report - published on:EP15.10.1998
ClassificationInternational:G06F17/50, G06F11/267
[2000/04]
Designated contracting statesAT,   BE,   CH,   CY,   DE,   DK,   ES,   FI,   FR,   GB,   GR,   IE,   IT,   LI,   LU,   NL,   PT,   SE [2000/04]
TitleGerman:VERFAHREN ZUM ENTWURF KOMPLEXER, DIGITALER UND INTEGRIERTER SCHALTUNGEN SOWIE SCHALTUNGSSTRUKTUR ZUR DURCHFÜHRUNG DES VERFAHRENS[2000/04]
English:METHOD FOR DESIGNING COMPLEX, DIGITAL AND INTEGRATED CIRCUITS AND A CIRCUIT STRUCTURE FOR CARRYING OUT SAID METHOD[2000/04]
French:PROCEDE POUR LA CONCEPTION DE CIRCUITS NUMERIQUES ET INTEGRES COMPLEXES ET STRUCTURE DE CIRCUIT POUR LA MISE EN OEUVRE DE CE PROCEDE[2000/04]
Entry into regional phase20.10.1999National basic fee paid 
20.10.1999Designation fee(s) paid 
20.10.1999Examination fee paid 
Examination procedure04.11.1998Request for preliminary examination filed
International Preliminary Examining Authority: EP
20.10.1999Amendment by applicant (claims and/or description)
20.10.1999Examination requested  [2000/04]
13.12.2001Despatch of a communication from the examining division (Time limit: M06)
24.06.2002Reply to a communication from the examining division
30.10.2002Despatch of a communication from the examining division (Time limit: M06)
12.03.2003Reply to a communication from the examining division
28.10.2003Despatch of a communication from the examining division (Time limit: M06)
07.05.2004Reply to a communication from the examining division
10.02.2005Despatch of a communication from the examining division (Time limit: M06)
17.08.2005Reply to a communication from the examining division
01.11.2006Application deemed to be withdrawn, date of legal effect  [2007/17]
05.12.2006Despatch of communication that the application is deemed to be withdrawn, reason: renewal fee not paid in time  [2007/17]
Fees paidRenewal fee
20.10.1999Renewal fee patent year 03
07.02.2001Renewal fee patent year 04
10.04.2002Renewal fee patent year 05
08.04.2003Renewal fee patent year 06
10.04.2004Renewal fee patent year 07
12.04.2005Renewal fee patent year 08
Penalty fee
Additional fee for renewal fee
30.04.200609   M06   Not yet paid
Cited inInternational search[X]  - GHOSH I ET AL, "DESIGN FOR HIERARCHICAL TESTABILITY OF RTL CIRCUITS OBTAINED BY BEHAVIORAL SYNTHESIS", INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, AUSTIN, OCT. 2 - 4, 1995, INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, (19951002), pages 173 - 179, XP000631910 [X] 1,2 * abstract *
 [A]  - VUAY NAGASAMY ET AL, "SPECIFICATION, PLANNING, AND SYNTHESIS", IEEE DESIGN & TEST OF COMPUTERS, (19920601), vol. 9, no. 2, pages 58 - 68, XP000306630 [A] 1-5 * page 60, column R, lines 20-37 * * page 62, column M, line 17 - column R, line 25; figure 2 *

DOI:   http://dx.doi.org/10.1109/54.143146
 [A]  - GAJSKI D D ET AL, "INTRODUCTION TO HIGH-LEVEL SYNTHESIS", IEEE DESIGN & TEST OF COMPUTERS, (19941221), vol. 11, no. 4, pages 44 - 54, XP000498505 [A] 1-7 * page 48, column R, line 16 - page 50, column M, line 15 *

DOI:   http://dx.doi.org/10.1109/54.329454
 [A]  - MAN DE H ET AL, "ARCHITECTURE-DRIVEN SYNTHESIS TECHNIQUES FOR VLSI INPLEMENTATION OFDSP ALGORITHMS", PROCEEDINGS OF THE IEEE, (19900201), vol. 78, no. 2, pages 319 - 335, XP000128907 [A] 1-21 * page 322, column R, lines 36-51; figure 2 *

DOI:   http://dx.doi.org/10.1109/5.52215
Examination US5493508