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Extract from the Register of European Patents

EP About this file: EP1010205

EP1010205 - LONE-ELECTRON CIRCUIT ARRANGEMENT, OPERATING MODE, AND APPLICATION FOR ADDING BINARY NUMBERS [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  14.12.2007
Database last updated on 25.05.2024
Most recent event   Tooltip21.11.2008Change - lapse in a contracting state
Updated state(s): FR
published on 24.12.2008  [2008/52]
Applicant(s)For all designated states
Infineon Technologies AG
St.-Martin-Strasse 53
81669 München / DE
[2007/06]
Former [2000/25]For all designated states
Infineon Technologies AG
St.-Martin-Strasse 53
81541 München / DE
Inventor(s)01 / RÖSNER, Wolfgang
Heinzelmännchenstrasse 2
D-81739 München / DE
02 / RAMCKE, Ties
Therese-Giehse-Allee 90
D-81739 München / DE
03 / RISCH, Lothar
Tizianstrasse 27
D-85579 Neubiberg / DE
[2000/25]
Representative(s)Jannig, Peter, et al
Jannig & Repkow
Patentanwälte PartG mbB
Klausenberg 20
86199 Augsburg / DE
[N/P]
Former [2001/19]Jannig, Peter, et al
Jannig & Repkow, Patentanwälte, Klausenberg 20
86199 Augsburg / DE
Former [2000/25]Zedlitz, Peter, Dipl.-Inf., et al
Patentanwalt, Postfach 22 13 17
80503 München / DE
Application number, filing date98952513.426.08.1998
[2000/25]
WO1998DE02521
Priority number, dateDE1997103811501.09.1997         Original published format: DE 19738115
[2000/25]
Filing languageDE
Procedural languageDE
PublicationType: A2 Application without search report
No.:WO9912212
Date:11.03.1999
Language:DE
[1999/10]
Type: A2 Application without search report 
No.:EP1010205
Date:21.06.2000
Language:DE
The application published by WIPO in one of the EPO official languages on 11.03.1999 takes the place of the publication of the European patent application.
[2000/25]
Type: B1 Patent specification 
No.:EP1010205
Date:07.02.2007
Language:DE
[2007/06]
Search report(s)International search report - published on:EP03.06.1999
ClassificationIPC:H01L29/76
[2000/25]
CPC:
G06F7/505 (EP,US); G06F7/502 (EP,US); H03K19/02 (EP,US);
G06F2207/4828 (EP,US); Y10S977/89 (EP,US); Y10S977/937 (EP,US);
Y10S977/94 (EP,US) (-)
Designated contracting statesDE,   FR,   GB,   IT [2000/25]
TitleGerman:SCHALTUNGSANORDNUNG MIT EINZELELEKTRON-BAUELEMENTEN, VERFAHREN ZU DEREN BETRIEB UND ANWENDUNG DES VERFAHRENS ZUR ADDITION VON BINÄRZAHLEN[2000/25]
English:LONE-ELECTRON CIRCUIT ARRANGEMENT, OPERATING MODE, AND APPLICATION FOR ADDING BINARY NUMBERS[2000/25]
French:CONFIGURATION DE CIRCUIT A COMPOSANTS UNI-ELECTRONIQUES, LEUR MODE DE FONCTIONNEMENT, ET APPLICATION POUR L'ADDITION DE NOMBRES BINAIRES[2000/25]
Entry into regional phase18.02.2000National basic fee paid 
18.02.2000Designation fee(s) paid 
18.02.2000Examination fee paid 
Examination procedure29.03.1999Request for preliminary examination filed
International Preliminary Examining Authority: EP
18.02.2000Examination requested  [2000/25]
23.11.2005Communication of intention to grant the patent
14.03.2006Fee for grant paid
14.03.2006Fee for publishing/printing paid
Opposition(s)08.11.2007No opposition filed within time limit [2008/03]
Fees paidRenewal fee
17.08.2000Renewal fee patent year 03
31.08.2001Renewal fee patent year 04
24.08.2002Renewal fee patent year 05
20.08.2003Renewal fee patent year 06
23.08.2004Renewal fee patent year 07
19.08.2005Renewal fee patent year 08
22.08.2006Renewal fee patent year 09
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipFR07.02.2007
GB07.02.2007
IT07.02.2007
[2008/52]
Former [2008/23]GB07.02.2007
IT07.02.2007
FR28.09.2007
Former [2008/16]GB07.02.2007
Cited inInternational search[AD]  - BENJAMIN S C ET AL, "A possible nanometer-scale computing device based on an adding cellular automaton", APPLIED PHYSICS LETTERS, 28 APRIL 1997, AIP, USA, ISSN 0003-6951, vol. 70, no. 17, pages 2321 - 2323, XP002098350 [AD] 1 * figure 1 *

DOI:   http://dx.doi.org/10.1063/1.118851
 [A]  - T. MOK ET AL., "A CHARGE-TRANSFER-DEVICE LOGIC CELL", SOLID STATE ELECTRONICS., OXFORD GB, (197411), vol. 17, no. 11, pages 1147 - 1154, XP002098351 [A] 1 * figure 5A *

DOI:   http://dx.doi.org/10.1016/0038-1101(74)90158-0
 [A]  - NOMOTO T ET AL, "Single electron-photon logic device using coupled quantum dots: computation with the Fock ground state", JOURNAL OF APPLIED PHYSICS, 1 JAN. 1996, AIP, USA, ISSN 0021-8979, vol. 79, no. 1, pages 291 - 300, XP002098352 [A] 1 * page 300, column L, paragraph 3; table I *

DOI:   http://dx.doi.org/10.1063/1.360943
 [A]  - IWAMURA H ET AL, "SINGLE-ELECTRON MAJORITY LOGIC CIRCUITS", IEICE TRANSACTIONS ON ELECTRONICS, (199801), vol. E81-C, no. 1, pages 42 - 48, XP000767487 [A] 1 * figures 1-3,7 *
Examination   - TUCKER J.R., J. APPL. PHYS., NY, (19921101), vol. 72, no. 9, pages 4399 - 4413, XP000315847

DOI:   http://dx.doi.org/10.1063/1.352206
    - ROSNER, MICROELECTRONICS ENGINEERING, (1995), vol. 27, pages 55 - 58
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.