Extract from the Register of European Patents

About this file: EP0940919

EP0940919 - Semiconductor integrated circuit device with built-in timing regulator for output signals [Right-click to bookmark this link]
StatusThe application has been withdrawn
Status updated on  19.09.2003
Database last updated on 19.04.2019
Most recent event   Tooltip25.07.2008Change - representativepublished on 27.08.2008  [2008/35]
Applicant(s)For all designated states
NEC Electronics Corporation
1753 Shimonumabe Nakahara-ku
Kawasaki, Kanagawa 211-8668 / JP
[N/P]
Former [2003/18]For all designated states
NEC Electronics Corporation
1753 Shimonumabe, Nakahara-ku
Kawasaki, Kanagawa 211-8668 / JP
Former [1999/36]For all designated states
NEC CORPORATION
7-1, Shiba 5-chome, Minato-ku
Tokyo / JP
Inventor(s)01 / Fujii, Takaharu
c/o NEC Corporation, 7-1, Shiba 5-chome
Minato-ku, Tokyo / JP
02 / Sakai, Toshichika
c/o NEC Corporation, 7-1, Shiba 5-chome
Minato-ku, Tokyo / JP
03 / Yashiba, Yasuo
c/o NEC Corporation, 7-1, Shiba 5-chome
Minato-ku, Tokyo / JP
[1999/36]
Representative(s)Vossius & Partner Patentanwälte Rechtsanwälte mbB
Siebertstrasse 3
81675 München / DE
[N/P]
Former [2008/35]Vossius & Partner
Siebertstrasse 3
81675 München / DE
Former [1999/36]VOSSIUS & PARTNER
Siebertstrasse 4
81675 München / DE
Application number, filing date99104210.202.03.1999
[1999/36]
Priority number, dateJP1998005071403.03.1998         Original published format: JP 5071498
[1999/36]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0940919
Date:08.09.1999
Language:EN
[1999/36]
Type: A3 Search report 
No.:EP0940919
Date:31.05.2000
[2000/22]
Search report(s)(Supplementary) European search report - dispatched on:EP13.04.2000
ClassificationInternational:H03K19/003, H03L7/07
[1999/36]
Designated contracting statesDE,   FR,   GB,   IT [2001/06]
Former [1999/36]AT,  BE,  CH,  CY,  DE,  DK,  ES,  FI,  FR,  GB,  GR,  IE,  IT,  LI,  LU,  MC,  NL,  PT,  SE 
TitleGerman:Integrierte Halbleiterschaltungsanordnung mit eingebautem Synchronisationsregler für Ausgangssignale[1999/36]
English:Semiconductor integrated circuit device with built-in timing regulator for output signals[1999/36]
French:Dispositif de circuit semi-conducteur intégré incorporant un régulateur de synchronisation des signaux de sortie[1999/36]
Examination procedure20.04.2000Examination requested  [2000/25]
10.09.2003Application withdrawn by applicant  [2003/45]
Fees paidRenewal fee
30.03.2001Renewal fee patent year 03
28.03.2002Renewal fee patent year 04
31.03.2003Renewal fee patent year 05
Documents cited:Search[X]US5485114  (FUNAKURA TERUHIKO [JP], et al) [X] 1 * column 11, line 6 - line 21; figure 5; claim 1 *;
 [X]US5486783  (BAUMERT ROBERT J [US], et al) [X] 1 * column A; figure 2; claim 1 *;
 [X]US5539344  (HATAKENAKA MAKOTO [JP]) [X] 1 * column 25, line 4 - line 59; figure 11; claim 1 *;
 [A]EP0662756  (OKI ELECTRIC IND CO LTD [JP]) [A] 2 * column A; figure 1; claim 1 *