Extract from the Register of European Patents

About this file: EP0984361

EP0984361 - Circuit arrangement for bias adjustment of a computer bus level [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  28.11.2008
Database last updated on 22.09.2017
Most recent event   Tooltip08.01.2010Lapse of the patent in a contracting statepublished on 10.02.2010  [2010/06]
Applicant(s)For all designated states
NXP B.V.
High Tech Campus 60
5656 AG Eindhoven / NL
[2007/30]
Former [2003/20]For:DE 
Philips Intellectual Property & Standards GmbH
Steindamm 94
20099 Hamburg / DE
For:FR  GB  IT 
Koninklijke Philips Electronics N.V.
Groenewoudseweg 1
5621 BA Eindhoven / NL
Former [2002/40]For:DE 
Philips Corporate Intellectual Property GmbH
20099 Hamburg / DE
For:FR  GB  IT 
Koninklijke Philips Electronics N.V.
Groenewoudseweg 1
5621 BA Eindhoven / NL
Former [2000/10]For:DE 
Philips Corporate Intellectual Property GmbH
Habsburgerallee 11
52064 Aachen / DE
For:FR  GB  IT 
Koninklijke Philips Electronics N.V.
Groenewoudseweg 1
5621 BA Eindhoven / NL
Inventor(s)01 / Mores, Robert Dr., Philips Corporate IP GmbH
Habsburgerallee 11
52064 Aachen / DE
[2000/10]
Representative(s)Volmer, Georg
Philips Intellectual Property & Standards GmbH
Postfach 50 04 42
52088 Aachen / DE
[N/P]
Former [2009/31]Volmer, Georg
Philips Intellectual Property & Standards GmbH Postfach 50 04 42
52088 Aachen / DE
Former [2000/10]Volmer, Georg, Dipl.-Ing.
Philips Corporate Intellectual Property, Habsburgerallee 11-13
52064 Aachen / DE
Application number, filing date99202835.701.09.1999
[2000/10]
Priority number, dateDE199814008603.09.1998         Original published format: DE 19840086
[2000/10]
Filing languageDE
Procedural languageDE
PublicationType: A2 Application without search report 
No.:EP0984361
Date:08.03.2000
Language:DE
[2000/10]
Type: A3 Search report 
No.:EP0984361
Date:15.03.2006
[2006/11]
Type: B1 Patent specification 
No.:EP0984361
Date:23.01.2008
Language:DE
[2008/04]
Search report(s)(Supplementary) European search report -
dispatched on:
EP26.01.2006
ClassificationInternational:G06F13/40
[2000/10]
Designated contracting statesDE,   FR,   GB,   IT [2006/47]
Former [2000/10]AT,  BE,  CH,  CY,  DE,  DK,  ES,  FI,  FR,  GB,  GR,  IE,  IT,  LI,  LU,  MC,  NL,  PT,  SE 
TitleGerman:Schaltungsanordnung zur BIAS Einstellung von Rechnerbuspegeln[2000/10]
English:Circuit arrangement for bias adjustment of a computer bus level[2000/10]
French:Dispositif de circuit pour l'ajustement de la polarisation de niveau de bus d'ordinateur[2000/10]
Examination procedure15.09.2006Examination requested  [2006/43]
11.10.2006Despatch of a communication from the examining division (Time limit: M04)
12.02.2007Reply to a communication from the examining division
29.05.2007Communication of intention to grant the patent
08.10.2007Fee for grant paid
08.10.2007Fee for publishing/printing paid
12.11.2007Despatch of communication that the application is deemed to be withdrawn, reason: fee for grant / fee for printing not paid in time
Opposition(s)24.10.2008No opposition filed within time limit [2009/01]
Request for further processing for:The application is deemed to be withdrawn due to failure to fulfill actions required for granting the patent
11.12.2007Request for further processing filed
11.12.2007Full payment received (date of receipt of payment)
Request granted
21.12.2007Decision despatched
Fees paidRenewal fee
01.10.2001Renewal fee patent year 03
30.09.2002Renewal fee patent year 04
30.09.2003Renewal fee patent year 05
30.09.2004Renewal fee patent year 06
30.09.2005Renewal fee patent year 07
02.10.2006Renewal fee patent year 08
01.10.2007Renewal fee patent year 09
Lapses during opposition  TooltipIT23.01.2008
[2010/06]
Documents cited:Search[A]US4220876  (RAY KENNETH I [US]) [A] 1-5 * abstract * * column 1, lines 33-39 *;
 [A]US5572658  (MOHR THOMAS [DE], et al) [A] 1-5 * abstract *