Extract from the Register of European Patents

About this file: EP1055170

EP1055170 - MICROPROCESSOR COMPRISING A SYNCHRONISING SYSTEM WITH AN EXPECTED ASYNCHRONOUS EVENT [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  17.03.2006
Database last updated on 16.06.2018
Most recent event   Tooltip21.03.2008Lapse of the patent in a contracting state
New state(s): IT
published on 23.04.2008  [2008/17]
Applicant(s)For all designated states
Inside Contactless
Bât. 11 A - Parc Club du Golf
13856 Aix en Provence Cedex 3 / FR
[2004/23]
Former [2000/48]For all designated states
Inside technologies
Pépinière Axone
69930 Saint-Clément-les-Places / FR
Inventor(s)01 / CHARRAT, Bruno, Bâtiment C
2 Lot des Marronniers 405, Avenue des Siffleuses
F-13090 Aix en Provence / FR
[2000/48]
Representative(s)Marchand, André , et al
OMNIPAT
24 Place des Martyrs de la Résistance
13100 Aix-en-Provence / FR
[N/P]
Former [2000/48]Marchand, André , et al
OMNIPAT, 24 Place des Martyrs de la Résistance
13100 Aix-en-Provence / FR
Application number, filing date99901627.226.01.1999
[2000/48]
WO1999FR00145
Priority number, dateFR1998000166812.02.1998         Original published format: FR 9801668
[2000/48]
Filing languageFR
Procedural languageFR
PublicationType: A1  Application with search report
No.:WO9941660
Date:19.08.1999
Language:FR
[1999/33]
Type: A1 Application with search report 
No.:EP1055170
Date:29.11.2000
Language:FR
The application has been published by WIPO in one of the EPO official languages on 19.08.1999
[2000/48]
Type: B1 Patent specification 
No.:EP1055170
Date:11.05.2005
Language:FR
[2005/19]
Search report(s)International search report - published on:EP19.08.1999
ClassificationInternational:G06F9/40
[2000/48]
Designated contracting statesCH,   DE,   ES,   FR,   GB,   IT,   LI,   NL [2000/48]
TitleGerman:MIKROPROZESSOR MIT EINEM SYSTEM ZUR SYNCHRONISATION MIT EINEM ERWARTETEN ASYNCHRONEN EREIGNIS[2000/48]
English:MICROPROCESSOR COMPRISING A SYNCHRONISING SYSTEM WITH AN EXPECTED ASYNCHRONOUS EVENT[2000/48]
French:MICROPROCESSEUR COMPORTANT UN SYSTEME DE SYNCHRONISATION AVEC UN EVENEMENT ASYNCHRONE ATTENDU[2000/48]
Entry into regional phase30.06.2000National basic fee paid 
30.06.2000Designation fee(s) paid 
30.06.2000Examination fee paid 
Examination procedure26.04.1999Request for preliminary examination filed
International Preliminary Examining Authority: EP
30.06.2000Examination requested  [2000/48]
26.11.2001Despatch of communication of intention to grant (Approval: No)
16.11.2004Despatch of communication of intention to grant (Approval: later approval)
22.11.2004Communication of intention to grant the patent
17.02.2005Fee for grant paid
17.02.2005Fee for publishing/printing paid
Opposition(s)14.02.2006No opposition filed within time limit [2006/18]
Fees paidRenewal fee
29.01.2001Renewal fee patent year 03
30.01.2002Renewal fee patent year 04
04.02.2003Renewal fee patent year 05
19.01.2004Renewal fee patent year 06
20.01.2005Renewal fee patent year 07
Penalty fee
Additional fee for renewal fee
31.01.200305   M06   Fee paid on   04.02.2003
Lapses during opposition  TooltipIT11.05.2005
NL11.05.2005
ES22.08.2005
CH31.01.2006
LI31.01.2006
[2008/17]
Former [2007/03]NL11.05.2005
ES22.08.2005
CH31.01.2006
LI31.01.2006
Former [2006/22]NL11.05.2005
ES22.08.2005
Former [2006/14]ES22.08.2005
Cited inInternational search[X]EP0395210  (ADVANCED MICRO DEVICES INC [US]) [X] 1-3,6-9,11-13 * page 3, line 4 - line 24 * * figure 1 *;
 [A]US5481230  (CHANG PAUL [US], et al) [A] 1-15 * column 3, line 31 - line 61 *
 [A]  - ANONYMOUS, "High Speed Input/Output Delay Counter. November 1973.", IBM TECHNICAL DISCLOSURE BULLETIN, New York, US, (197311), vol. 16, no. 6, pages 1871 - 1873, XP002084545 [A] 1-15 * the whole document *