-
EP1054345
European procedure
- EP About this file
- EP Legal status
- EP Federated register
- EP Event history
- EP Citations
- EP Patent family
- EP All documents
Extract from the Register of European Patents
EP About this file: EP1054345
| EP1054345 - Digital analysis of the external clock frequency of chipcards [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 02.05.2008 Database last updated on 11.09.2024 | Most recent event Tooltip | 02.05.2008 | Application deemed to be withdrawn | published on 04.06.2008 [2008/23] | Applicant(s) | For all designated states Beta Research GmbH Betastrasse 1 85774 Unterföhring / DE | [2000/47] | Inventor(s) | 01 /
Mester, Roland Friedenspromenade 17 81827 München / DE | [2000/47] | Representative(s) | Heselberger, Johannes, et al Bardehle Pagenberg Partnerschaft mbB Patentanwälte, Rechtsanwälte Prinzregentenplatz 7 81675 München / DE | [N/P] |
| Former [2000/47] | Heselberger, Johannes, et al Bardehle, Pagenberg, Dost, Altenburg, Geissler, Isenbruck, Galileiplatz 1 81679 München / DE | Application number, filing date | 00110137.7 | 11.05.2000 | [2000/47] | Priority number, date | DE1999123231 | 20.05.1999 Original published format: DE 19923231 | [2000/47] | Filing language | DE | Procedural language | DE | Publication | Type: | A2 Application without search report | No.: | EP1054345 | Date: | 22.11.2000 | Language: | DE | [2000/47] | Type: | A3 Search report | No.: | EP1054345 | Date: | 19.12.2001 | [2001/51] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 06.11.2001 | Classification | IPC: | G06K19/073 | [2000/47] | CPC: |
G06K19/073 (EP);
G06K19/07363 (EP);
G06K19/07372 (EP)
| Designated contracting states | AT, CH, DE, FR, GB, LI [2002/37] |
| Former [2000/47] | AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE | Title | German: | Digitale Analyse der externen Taktfrequenz von Chipkarten | [2000/47] | English: | Digital analysis of the external clock frequency of chipcards | [2000/47] | French: | Analyse digitale de la fréquence d'horloge externe des cartes à puce | [2000/47] | Examination procedure | 19.06.2002 | Examination requested [2002/34] | 02.08.2007 | Despatch of a communication from the examining division (Time limit: M04) | 13.12.2007 | Application deemed to be withdrawn, date of legal effect [2008/23] | 16.01.2008 | Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time [2008/23] | Fees paid | Renewal fee | 28.05.2002 | Renewal fee patent year 03 | 28.05.2003 | Renewal fee patent year 04 | 25.05.2004 | Renewal fee patent year 05 | 12.05.2005 | Renewal fee patent year 06 | 23.03.2006 | Renewal fee patent year 07 | 14.05.2007 | Renewal fee patent year 08 |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]WO9848523 (KONINKL PHILIPS ELECTRONICS NV [NL], et al) [X] 1,5 * page 11, lines 12-23; figure 1 *; | [A]WO9734254 (SIEMENS AG [DE], et al) [A] 1,5 * page 6, lines 11-23 *; | [A]US4590440 (HAQUE YUSUF A [US], et al) [A] 1,5 * column 4, line 35 - column 6, line 18; figures 7-9 *; | [A]US5619155 (WANG SONG-TINE [TW]) [A] 1,5 * column 3, line 66 - column 4, line 20 * | [A] - KOEMMERLING O ET AL, "DESIGN PRINCIPLES FOR TAMPER-RESISTANT SMARTCARD PROCESSORS", USENIX WORKSHOP ON SMARTCARD TECHNOLOGY, XX, XX, (19990510), pages 9 - 20, XP001007283 [A] 1,5 * page 17, column 2, paragraphs 2-4 * |